1 /**************************************************************************//**
2 * @file cmsis_armcc.h
3 * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
4 * @version V5.0.5
5 * @date 14. December 2018
6 ******************************************************************************/
7 /*
8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25 #ifndef __CMSIS_ARMCC_H
26 #define __CMSIS_ARMCC_H
27
28
29 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
30 #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
31 #endif
32
33 /* CMSIS compiler control architecture macros */
34 #if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
35 (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
36 #define __ARM_ARCH_6M__ 1
37 #endif
38
39 #if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
40 #define __ARM_ARCH_7M__ 1
41 #endif
42
43 #if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
44 #define __ARM_ARCH_7EM__ 1
45 #endif
46
47 /* __ARM_ARCH_8M_BASE__ not applicable */
48 /* __ARM_ARCH_8M_MAIN__ not applicable */
49
50 /* CMSIS compiler control DSP macros */
51 #if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
52 #define __ARM_FEATURE_DSP 1
53 #endif
54
55 /* CMSIS compiler specific defines */
56 #ifndef __ASM
57 #define __ASM __asm
58 #endif
59 #ifndef __INLINE
60 #define __INLINE __inline
61 #endif
62 #ifndef __STATIC_INLINE
63 #define __STATIC_INLINE static __inline
64 #endif
65 #ifndef __STATIC_FORCEINLINE
66 #define __STATIC_FORCEINLINE static __forceinline
67 #endif
68 #ifndef __NO_RETURN
69 #define __NO_RETURN __declspec(noreturn)
70 #endif
71 #ifndef __USED
72 #define __USED __attribute__((used))
73 #endif
74 #ifndef __WEAK
75 #define __WEAK __attribute__((weak))
76 #endif
77 #ifndef __PACKED
78 #define __PACKED __attribute__((packed))
79 #endif
80 #ifndef __PACKED_STRUCT
81 #define __PACKED_STRUCT __packed struct
82 #endif
83 #ifndef __PACKED_UNION
84 #define __PACKED_UNION __packed union
85 #endif
86 #ifndef __UNALIGNED_UINT32 /* deprecated */
87 #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
88 #endif
89 #ifndef __UNALIGNED_UINT16_WRITE
90 #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
91 #endif
92 #ifndef __UNALIGNED_UINT16_READ
93 #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
94 #endif
95 #ifndef __UNALIGNED_UINT32_WRITE
96 #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
97 #endif
98 #ifndef __UNALIGNED_UINT32_READ
99 #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
100 #endif
101 #ifndef __ALIGNED
102 #define __ALIGNED(x) __attribute__((aligned(x)))
103 #endif
104 #ifndef __RESTRICT
105 #define __RESTRICT __restrict
106 #endif
107
108 /* ########################### Core Function Access ########################### */
109 /** \ingroup CMSIS_Core_FunctionInterface
110 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
111 @{
112 */
113
114 /**
115 \brief Enable IRQ Interrupts
116 \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
117 Can only be executed in Privileged modes.
118 */
119 /* intrinsic void __enable_irq(); */
120
121
122 /**
123 \brief Disable IRQ Interrupts
124 \details Disables IRQ interrupts by setting the I-bit in the CPSR.
125 Can only be executed in Privileged modes.
126 */
127 /* intrinsic void __disable_irq(); */
128
129 /**
130 \brief Get Control Register
131 \details Returns the content of the Control Register.
132 \return Control Register value
133 */
__get_CONTROL(void)134 __STATIC_INLINE uint32_t __get_CONTROL(void)
135 {
136 register uint32_t __regControl __ASM("control");
137 return (__regControl);
138 }
139
140
141 /**
142 \brief Set Control Register
143 \details Writes the given value to the Control Register.
144 \param [in] control Control Register value to set
145 */
__set_CONTROL(uint32_t control)146 __STATIC_INLINE void __set_CONTROL(uint32_t control)
147 {
148 register uint32_t __regControl __ASM("control");
149 __regControl = control;
150 }
151
152
153 /**
154 \brief Get IPSR Register
155 \details Returns the content of the IPSR Register.
156 \return IPSR Register value
157 */
__get_IPSR(void)158 __STATIC_INLINE uint32_t __get_IPSR(void)
159 {
160 register uint32_t __regIPSR __ASM("ipsr");
161 return (__regIPSR);
162 }
163
164
165 /**
166 \brief Get APSR Register
167 \details Returns the content of the APSR Register.
168 \return APSR Register value
169 */
__get_APSR(void)170 __STATIC_INLINE uint32_t __get_APSR(void)
171 {
172 register uint32_t __regAPSR __ASM("apsr");
173 return (__regAPSR);
174 }
175
176
177 /**
178 \brief Get xPSR Register
179 \details Returns the content of the xPSR Register.
180 \return xPSR Register value
181 */
__get_xPSR(void)182 __STATIC_INLINE uint32_t __get_xPSR(void)
183 {
184 register uint32_t __regXPSR __ASM("xpsr");
185 return (__regXPSR);
186 }
187
188
189 /**
190 \brief Get Process Stack Pointer
191 \details Returns the current value of the Process Stack Pointer (PSP).
192 \return PSP Register value
193 */
__get_PSP(void)194 __STATIC_INLINE uint32_t __get_PSP(void)
195 {
196 register uint32_t __regProcessStackPointer __ASM("psp");
197 return (__regProcessStackPointer);
198 }
199
200
201 /**
202 \brief Set Process Stack Pointer
203 \details Assigns the given value to the Process Stack Pointer (PSP).
204 \param [in] topOfProcStack Process Stack Pointer value to set
205 */
__set_PSP(uint32_t topOfProcStack)206 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
207 {
208 register uint32_t __regProcessStackPointer __ASM("psp");
209 __regProcessStackPointer = topOfProcStack;
210 }
211
212
213 /**
214 \brief Get Main Stack Pointer
215 \details Returns the current value of the Main Stack Pointer (MSP).
216 \return MSP Register value
217 */
__get_MSP(void)218 __STATIC_INLINE uint32_t __get_MSP(void)
219 {
220 register uint32_t __regMainStackPointer __ASM("msp");
221 return (__regMainStackPointer);
222 }
223
224
225 /**
226 \brief Set Main Stack Pointer
227 \details Assigns the given value to the Main Stack Pointer (MSP).
228 \param [in] topOfMainStack Main Stack Pointer value to set
229 */
__set_MSP(uint32_t topOfMainStack)230 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
231 {
232 register uint32_t __regMainStackPointer __ASM("msp");
233 __regMainStackPointer = topOfMainStack;
234 }
235
236
237 /**
238 \brief Get Priority Mask
239 \details Returns the current state of the priority mask bit from the Priority Mask Register.
240 \return Priority Mask value
241 */
__get_PRIMASK(void)242 __STATIC_INLINE uint32_t __get_PRIMASK(void)
243 {
244 register uint32_t __regPriMask __ASM("primask");
245 return (__regPriMask);
246 }
247
248
249 /**
250 \brief Set Priority Mask
251 \details Assigns the given value to the Priority Mask Register.
252 \param [in] priMask Priority Mask
253 */
__set_PRIMASK(uint32_t priMask)254 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
255 {
256 register uint32_t __regPriMask __ASM("primask");
257 __regPriMask = (priMask);
258 }
259
260
261 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
262 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
263
264 /**
265 \brief Enable FIQ
266 \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
267 Can only be executed in Privileged modes.
268 */
269 #define __enable_fault_irq __enable_fiq
270
271
272 /**
273 \brief Disable FIQ
274 \details Disables FIQ interrupts by setting the F-bit in the CPSR.
275 Can only be executed in Privileged modes.
276 */
277 #define __disable_fault_irq __disable_fiq
278
279
280 /**
281 \brief Get Base Priority
282 \details Returns the current value of the Base Priority register.
283 \return Base Priority register value
284 */
__get_BASEPRI(void)285 __STATIC_INLINE uint32_t __get_BASEPRI(void)
286 {
287 register uint32_t __regBasePri __ASM("basepri");
288 return (__regBasePri);
289 }
290
291
292 /**
293 \brief Set Base Priority
294 \details Assigns the given value to the Base Priority register.
295 \param [in] basePri Base Priority value to set
296 */
__set_BASEPRI(uint32_t basePri)297 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
298 {
299 register uint32_t __regBasePri __ASM("basepri");
300 __regBasePri = (basePri & 0xFFU);
301 }
302
303
304 /**
305 \brief Set Base Priority with condition
306 \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
307 or the new value increases the BASEPRI priority level.
308 \param [in] basePri Base Priority value to set
309 */
__set_BASEPRI_MAX(uint32_t basePri)310 __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
311 {
312 register uint32_t __regBasePriMax __ASM("basepri_max");
313 __regBasePriMax = (basePri & 0xFFU);
314 }
315
316
317 /**
318 \brief Get Fault Mask
319 \details Returns the current value of the Fault Mask register.
320 \return Fault Mask register value
321 */
__get_FAULTMASK(void)322 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
323 {
324 register uint32_t __regFaultMask __ASM("faultmask");
325 return (__regFaultMask);
326 }
327
328
329 /**
330 \brief Set Fault Mask
331 \details Assigns the given value to the Fault Mask register.
332 \param [in] faultMask Fault Mask value to set
333 */
__set_FAULTMASK(uint32_t faultMask)334 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
335 {
336 register uint32_t __regFaultMask __ASM("faultmask");
337 __regFaultMask = (faultMask & (uint32_t)1U);
338 }
339
340 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
341 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
342
343
344 /**
345 \brief Get FPSCR
346 \details Returns the current value of the Floating Point Status/Control register.
347 \return Floating Point Status/Control register value
348 */
__get_FPSCR(void)349 __STATIC_INLINE uint32_t __get_FPSCR(void)
350 {
351 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
352 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
353 register uint32_t __regfpscr __ASM("fpscr");
354 return (__regfpscr);
355 #else
356 return (0U);
357 #endif
358 }
359
360
361 /**
362 \brief Set FPSCR
363 \details Assigns the given value to the Floating Point Status/Control register.
364 \param [in] fpscr Floating Point Status/Control value to set
365 */
__set_FPSCR(uint32_t fpscr)366 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
367 {
368 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
369 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
370 register uint32_t __regfpscr __ASM("fpscr");
371 __regfpscr = (fpscr);
372 #else
373 (void)fpscr;
374 #endif
375 }
376
377
378 /*@} end of CMSIS_Core_RegAccFunctions */
379
380
381 /* ########################## Core Instruction Access ######################### */
382 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
383 Access to dedicated instructions
384 @{
385 */
386
387 /**
388 \brief No Operation
389 \details No Operation does nothing. This instruction can be used for code alignment purposes.
390 */
391 #define __NOP __nop
392
393
394 /**
395 \brief Wait For Interrupt
396 \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
397 */
398 #define __WFI __wfi
399
400
401 /**
402 \brief Wait For Event
403 \details Wait For Event is a hint instruction that permits the processor to enter
404 a low-power state until one of a number of events occurs.
405 */
406 #define __WFE __wfe
407
408
409 /**
410 \brief Send Event
411 \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
412 */
413 #define __SEV __sev
414
415
416 /**
417 \brief Instruction Synchronization Barrier
418 \details Instruction Synchronization Barrier flushes the pipeline in the processor,
419 so that all instructions following the ISB are fetched from cache or memory,
420 after the instruction has been completed.
421 */
422 #define __ISB() do {\
423 __schedule_barrier();\
424 __isb(0xF);\
425 __schedule_barrier();\
426 } while (0U)
427
428 /**
429 \brief Data Synchronization Barrier
430 \details Acts as a special kind of Data Memory Barrier.
431 It completes when all explicit memory accesses before this instruction complete.
432 */
433 #define __DSB() do {\
434 __schedule_barrier();\
435 __dsb(0xF);\
436 __schedule_barrier();\
437 } while (0U)
438
439 /**
440 \brief Data Memory Barrier
441 \details Ensures the apparent order of the explicit memory operations before
442 and after the instruction, without ensuring their completion.
443 */
444 #define __DMB() do {\
445 __schedule_barrier();\
446 __dmb(0xF);\
447 __schedule_barrier();\
448 } while (0U)
449
450
451 /**
452 \brief Reverse byte order (32 bit)
453 \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
454 \param [in] value Value to reverse
455 \return Reversed value
456 */
457 #define __REV __rev
458
459
460 /**
461 \brief Reverse byte order (16 bit)
462 \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
463 \param [in] value Value to reverse
464 \return Reversed value
465 */
466 #ifndef __NO_EMBEDDED_ASM
__REV16(uint32_t value)467 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
468 {
469 rev16 r0, r0
470 bx lr
471 }
472 #endif
473
474
475 /**
476 \brief Reverse byte order (16 bit)
477 \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
478 \param [in] value Value to reverse
479 \return Reversed value
480 */
481 #ifndef __NO_EMBEDDED_ASM
__REVSH(int16_t value)482 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
483 {
484 revsh r0, r0
485 bx lr
486 }
487 #endif
488
489
490 /**
491 \brief Rotate Right in unsigned value (32 bit)
492 \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
493 \param [in] op1 Value to rotate
494 \param [in] op2 Number of Bits to rotate
495 \return Rotated value
496 */
497 #define __ROR __ror
498
499
500 /**
501 \brief Breakpoint
502 \details Causes the processor to enter Debug state.
503 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
504 \param [in] value is ignored by the processor.
505 If required, a debugger can use it to store additional information about the breakpoint.
506 */
507 #define __BKPT(value) __breakpoint(value)
508
509
510 /**
511 \brief Reverse bit order of value
512 \details Reverses the bit order of the given value.
513 \param [in] value Value to reverse
514 \return Reversed value
515 */
516 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
517 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
518 #define __RBIT __rbit
519 #else
__RBIT(uint32_t value)520 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
521 {
522 uint32_t result;
523 uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
524
525 result = value; /* r will be reversed bits of v; first get LSB of v */
526 for (value >>= 1U; value != 0U; value >>= 1U)
527 {
528 result <<= 1U;
529 result |= value & 1U;
530 s--;
531 }
532 result <<= s; /* shift when v's highest bits are zero */
533 return result;
534 }
535 #endif
536
537
538 /**
539 \brief Count leading zeros
540 \details Counts the number of leading zeros of a data value.
541 \param [in] value Value to count the leading zeros
542 \return number of leading zeros in value
543 */
544 #define __CLZ __clz
545
546
547 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
548 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
549
550 /**
551 \brief LDR Exclusive (8 bit)
552 \details Executes a exclusive LDR instruction for 8 bit value.
553 \param [in] ptr Pointer to data
554 \return value of type uint8_t at (*ptr)
555 */
556 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
557 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
558 #else
559 #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
560 #endif
561
562
563 /**
564 \brief LDR Exclusive (16 bit)
565 \details Executes a exclusive LDR instruction for 16 bit values.
566 \param [in] ptr Pointer to data
567 \return value of type uint16_t at (*ptr)
568 */
569 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
570 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
571 #else
572 #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
573 #endif
574
575
576 /**
577 \brief LDR Exclusive (32 bit)
578 \details Executes a exclusive LDR instruction for 32 bit values.
579 \param [in] ptr Pointer to data
580 \return value of type uint32_t at (*ptr)
581 */
582 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
583 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
584 #else
585 #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
586 #endif
587
588
589 /**
590 \brief STR Exclusive (8 bit)
591 \details Executes a exclusive STR instruction for 8 bit values.
592 \param [in] value Value to store
593 \param [in] ptr Pointer to location
594 \return 0 Function succeeded
595 \return 1 Function failed
596 */
597 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
598 #define __STREXB(value, ptr) __strex(value, ptr)
599 #else
600 #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
601 #endif
602
603
604 /**
605 \brief STR Exclusive (16 bit)
606 \details Executes a exclusive STR instruction for 16 bit values.
607 \param [in] value Value to store
608 \param [in] ptr Pointer to location
609 \return 0 Function succeeded
610 \return 1 Function failed
611 */
612 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
613 #define __STREXH(value, ptr) __strex(value, ptr)
614 #else
615 #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
616 #endif
617
618
619 /**
620 \brief STR Exclusive (32 bit)
621 \details Executes a exclusive STR instruction for 32 bit values.
622 \param [in] value Value to store
623 \param [in] ptr Pointer to location
624 \return 0 Function succeeded
625 \return 1 Function failed
626 */
627 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
628 #define __STREXW(value, ptr) __strex(value, ptr)
629 #else
630 #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
631 #endif
632
633
634 /**
635 \brief Remove the exclusive lock
636 \details Removes the exclusive lock which is created by LDREX.
637 */
638 #define __CLREX __clrex
639
640
641 /**
642 \brief Signed Saturate
643 \details Saturates a signed value.
644 \param [in] value Value to be saturated
645 \param [in] sat Bit position to saturate to (1..32)
646 \return Saturated value
647 */
648 #define __SSAT __ssat
649
650
651 /**
652 \brief Unsigned Saturate
653 \details Saturates an unsigned value.
654 \param [in] value Value to be saturated
655 \param [in] sat Bit position to saturate to (0..31)
656 \return Saturated value
657 */
658 #define __USAT __usat
659
660
661 /**
662 \brief Rotate Right with Extend (32 bit)
663 \details Moves each bit of a bitstring right by one bit.
664 The carry input is shifted in at the left end of the bitstring.
665 \param [in] value Value to rotate
666 \return Rotated value
667 */
668 #ifndef __NO_EMBEDDED_ASM
__RRX(uint32_t value)669 __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
670 {
671 rrx r0, r0
672 bx lr
673 }
674 #endif
675
676
677 /**
678 \brief LDRT Unprivileged (8 bit)
679 \details Executes a Unprivileged LDRT instruction for 8 bit value.
680 \param [in] ptr Pointer to data
681 \return value of type uint8_t at (*ptr)
682 */
683 #define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
684
685
686 /**
687 \brief LDRT Unprivileged (16 bit)
688 \details Executes a Unprivileged LDRT instruction for 16 bit values.
689 \param [in] ptr Pointer to data
690 \return value of type uint16_t at (*ptr)
691 */
692 #define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
693
694
695 /**
696 \brief LDRT Unprivileged (32 bit)
697 \details Executes a Unprivileged LDRT instruction for 32 bit values.
698 \param [in] ptr Pointer to data
699 \return value of type uint32_t at (*ptr)
700 */
701 #define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
702
703
704 /**
705 \brief STRT Unprivileged (8 bit)
706 \details Executes a Unprivileged STRT instruction for 8 bit values.
707 \param [in] value Value to store
708 \param [in] ptr Pointer to location
709 */
710 #define __STRBT(value, ptr) __strt(value, ptr)
711
712
713 /**
714 \brief STRT Unprivileged (16 bit)
715 \details Executes a Unprivileged STRT instruction for 16 bit values.
716 \param [in] value Value to store
717 \param [in] ptr Pointer to location
718 */
719 #define __STRHT(value, ptr) __strt(value, ptr)
720
721
722 /**
723 \brief STRT Unprivileged (32 bit)
724 \details Executes a Unprivileged STRT instruction for 32 bit values.
725 \param [in] value Value to store
726 \param [in] ptr Pointer to location
727 */
728 #define __STRT(value, ptr) __strt(value, ptr)
729
730 #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
731 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
732
733 /**
734 \brief Signed Saturate
735 \details Saturates a signed value.
736 \param [in] value Value to be saturated
737 \param [in] sat Bit position to saturate to (1..32)
738 \return Saturated value
739 */
__SSAT(int32_t val,uint32_t sat)740 __attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
741 {
742 if ((sat >= 1U) && (sat <= 32U))
743 {
744 const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
745 const int32_t min = -1 - max ;
746 if (val > max)
747 {
748 return max;
749 }
750 else if (val < min)
751 {
752 return min;
753 }
754 }
755 return val;
756 }
757
758 /**
759 \brief Unsigned Saturate
760 \details Saturates an unsigned value.
761 \param [in] value Value to be saturated
762 \param [in] sat Bit position to saturate to (0..31)
763 \return Saturated value
764 */
__USAT(int32_t val,uint32_t sat)765 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
766 {
767 if (sat <= 31U)
768 {
769 const uint32_t max = ((1U << sat) - 1U);
770 if (val > (int32_t)max)
771 {
772 return max;
773 }
774 else if (val < 0)
775 {
776 return 0U;
777 }
778 }
779 return (uint32_t)val;
780 }
781
782 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
783 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
784
785 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
786
787
788 /* ################### Compiler specific Intrinsics ########################### */
789 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
790 Access to dedicated SIMD instructions
791 @{
792 */
793
794 #if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
795
796 #define __SADD8 __sadd8
797 #define __QADD8 __qadd8
798 #define __SHADD8 __shadd8
799 #define __UADD8 __uadd8
800 #define __UQADD8 __uqadd8
801 #define __UHADD8 __uhadd8
802 #define __SSUB8 __ssub8
803 #define __QSUB8 __qsub8
804 #define __SHSUB8 __shsub8
805 #define __USUB8 __usub8
806 #define __UQSUB8 __uqsub8
807 #define __UHSUB8 __uhsub8
808 #define __SADD16 __sadd16
809 #define __QADD16 __qadd16
810 #define __SHADD16 __shadd16
811 #define __UADD16 __uadd16
812 #define __UQADD16 __uqadd16
813 #define __UHADD16 __uhadd16
814 #define __SSUB16 __ssub16
815 #define __QSUB16 __qsub16
816 #define __SHSUB16 __shsub16
817 #define __USUB16 __usub16
818 #define __UQSUB16 __uqsub16
819 #define __UHSUB16 __uhsub16
820 #define __SASX __sasx
821 #define __QASX __qasx
822 #define __SHASX __shasx
823 #define __UASX __uasx
824 #define __UQASX __uqasx
825 #define __UHASX __uhasx
826 #define __SSAX __ssax
827 #define __QSAX __qsax
828 #define __SHSAX __shsax
829 #define __USAX __usax
830 #define __UQSAX __uqsax
831 #define __UHSAX __uhsax
832 #define __USAD8 __usad8
833 #define __USADA8 __usada8
834 #define __SSAT16 __ssat16
835 #define __USAT16 __usat16
836 #define __UXTB16 __uxtb16
837 #define __UXTAB16 __uxtab16
838 #define __SXTB16 __sxtb16
839 #define __SXTAB16 __sxtab16
840 #define __SMUAD __smuad
841 #define __SMUADX __smuadx
842 #define __SMLAD __smlad
843 #define __SMLADX __smladx
844 #define __SMLALD __smlald
845 #define __SMLALDX __smlaldx
846 #define __SMUSD __smusd
847 #define __SMUSDX __smusdx
848 #define __SMLSD __smlsd
849 #define __SMLSDX __smlsdx
850 #define __SMLSLD __smlsld
851 #define __SMLSLDX __smlsldx
852 #define __SEL __sel
853 #define __QADD __qadd
854 #define __QSUB __qsub
855
856 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
857 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
858
859 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
860 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
861
862 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
863 ((int64_t)(ARG3) << 32U) ) >> 32U))
864
865 #endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
866 /*@} end of group CMSIS_SIMD_intrinsics */
867
868
869 #endif /* __CMSIS_ARMCC_H */
870