1 //***************************************************************************** 2 // 3 // hw_aes.h - Macros used when accessing the AES hardware. 4 // 5 // Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Redistribution and use in source and binary forms, with or without 9 // modification, are permitted provided that the following conditions 10 // are met: 11 // 12 // Redistributions of source code must retain the above copyright 13 // notice, this list of conditions and the following disclaimer. 14 // 15 // Redistributions in binary form must reproduce the above copyright 16 // notice, this list of conditions and the following disclaimer in the 17 // documentation and/or other materials provided with the 18 // distribution. 19 // 20 // Neither the name of Texas Instruments Incorporated nor the names of 21 // its contributors may be used to endorse or promote products derived 22 // from this software without specific prior written permission. 23 // 24 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 // 36 //***************************************************************************** 37 38 #ifndef __HW_AES_H__ 39 #define __HW_AES_H__ 40 41 //***************************************************************************** 42 // 43 // The following are defines for the AES register offsets. 44 // 45 //***************************************************************************** 46 #define AES_O_KEY2_6 0x00000000 // AES Key 2_6 47 #define AES_O_KEY2_7 0x00000004 // AES Key 2_7 48 #define AES_O_KEY2_4 0x00000008 // AES Key 2_4 49 #define AES_O_KEY2_5 0x0000000C // AES Key 2_5 50 #define AES_O_KEY2_2 0x00000010 // AES Key 2_2 51 #define AES_O_KEY2_3 0x00000014 // AES Key 2_3 52 #define AES_O_KEY2_0 0x00000018 // AES Key 2_0 53 #define AES_O_KEY2_1 0x0000001C // AES Key 2_1 54 #define AES_O_KEY1_6 0x00000020 // AES Key 1_6 55 #define AES_O_KEY1_7 0x00000024 // AES Key 1_7 56 #define AES_O_KEY1_4 0x00000028 // AES Key 1_4 57 #define AES_O_KEY1_5 0x0000002C // AES Key 1_5 58 #define AES_O_KEY1_2 0x00000030 // AES Key 1_2 59 #define AES_O_KEY1_3 0x00000034 // AES Key 1_3 60 #define AES_O_KEY1_0 0x00000038 // AES Key 1_0 61 #define AES_O_KEY1_1 0x0000003C // AES Key 1_1 62 #define AES_O_IV_IN_0 0x00000040 // AES Initialization Vector Input 63 // 0 64 #define AES_O_IV_IN_1 0x00000044 // AES Initialization Vector Input 65 // 1 66 #define AES_O_IV_IN_2 0x00000048 // AES Initialization Vector Input 67 // 2 68 #define AES_O_IV_IN_3 0x0000004C // AES Initialization Vector Input 69 // 3 70 #define AES_O_CTRL 0x00000050 // AES Control 71 #define AES_O_C_LENGTH_0 0x00000054 // AES Crypto Data Length 0 72 #define AES_O_C_LENGTH_1 0x00000058 // AES Crypto Data Length 1 73 #define AES_O_AUTH_LENGTH 0x0000005C // AES Authentication Data Length 74 #define AES_O_DATA_IN_0 0x00000060 // AES Data RW Plaintext/Ciphertext 75 // 0 76 #define AES_O_DATA_IN_1 0x00000064 // AES Data RW Plaintext/Ciphertext 77 // 1 78 #define AES_O_DATA_IN_2 0x00000068 // AES Data RW Plaintext/Ciphertext 79 // 2 80 #define AES_O_DATA_IN_3 0x0000006C // AES Data RW Plaintext/Ciphertext 81 // 3 82 #define AES_O_TAG_OUT_0 0x00000070 // AES Hash Tag Out 0 83 #define AES_O_TAG_OUT_1 0x00000074 // AES Hash Tag Out 1 84 #define AES_O_TAG_OUT_2 0x00000078 // AES Hash Tag Out 2 85 #define AES_O_TAG_OUT_3 0x0000007C // AES Hash Tag Out 3 86 #define AES_O_REVISION 0x00000080 // AES IP Revision Identifier 87 #define AES_O_SYSCONFIG 0x00000084 // AES System Configuration 88 #define AES_O_SYSSTATUS 0x00000088 // AES System Status 89 #define AES_O_IRQSTATUS 0x0000008C // AES Interrupt Status 90 #define AES_O_IRQENABLE 0x00000090 // AES Interrupt Enable 91 #define AES_O_DIRTYBITS 0x00000094 // AES Dirty Bits 92 #define AES_O_DMAIM 0xFFFFA020 // AES DMA Interrupt Mask 93 #define AES_O_DMARIS 0xFFFFA024 // AES DMA Raw Interrupt Status 94 #define AES_O_DMAMIS 0xFFFFA028 // AES DMA Masked Interrupt Status 95 #define AES_O_DMAIC 0xFFFFA02C // AES DMA Interrupt Clear 96 97 //***************************************************************************** 98 // 99 // The following are defines for the bit fields in the AES_O_KEY2_6 register. 100 // 101 //***************************************************************************** 102 #define AES_KEY2_6_KEY_M 0xFFFFFFFF // Key Data 103 #define AES_KEY2_6_KEY_S 0 104 105 //***************************************************************************** 106 // 107 // The following are defines for the bit fields in the AES_O_KEY2_7 register. 108 // 109 //***************************************************************************** 110 #define AES_KEY2_7_KEY_M 0xFFFFFFFF // Key Data 111 #define AES_KEY2_7_KEY_S 0 112 113 //***************************************************************************** 114 // 115 // The following are defines for the bit fields in the AES_O_KEY2_4 register. 116 // 117 //***************************************************************************** 118 #define AES_KEY2_4_KEY_M 0xFFFFFFFF // Key Data 119 #define AES_KEY2_4_KEY_S 0 120 121 //***************************************************************************** 122 // 123 // The following are defines for the bit fields in the AES_O_KEY2_5 register. 124 // 125 //***************************************************************************** 126 #define AES_KEY2_5_KEY_M 0xFFFFFFFF // Key Data 127 #define AES_KEY2_5_KEY_S 0 128 129 //***************************************************************************** 130 // 131 // The following are defines for the bit fields in the AES_O_KEY2_2 register. 132 // 133 //***************************************************************************** 134 #define AES_KEY2_2_KEY_M 0xFFFFFFFF // Key Data 135 #define AES_KEY2_2_KEY_S 0 136 137 //***************************************************************************** 138 // 139 // The following are defines for the bit fields in the AES_O_KEY2_3 register. 140 // 141 //***************************************************************************** 142 #define AES_KEY2_3_KEY_M 0xFFFFFFFF // Key Data 143 #define AES_KEY2_3_KEY_S 0 144 145 //***************************************************************************** 146 // 147 // The following are defines for the bit fields in the AES_O_KEY2_0 register. 148 // 149 //***************************************************************************** 150 #define AES_KEY2_0_KEY_M 0xFFFFFFFF // Key Data 151 #define AES_KEY2_0_KEY_S 0 152 153 //***************************************************************************** 154 // 155 // The following are defines for the bit fields in the AES_O_KEY2_1 register. 156 // 157 //***************************************************************************** 158 #define AES_KEY2_1_KEY_M 0xFFFFFFFF // Key Data 159 #define AES_KEY2_1_KEY_S 0 160 161 //***************************************************************************** 162 // 163 // The following are defines for the bit fields in the AES_O_KEY1_6 register. 164 // 165 //***************************************************************************** 166 #define AES_KEY1_6_KEY_M 0xFFFFFFFF // Key Data 167 #define AES_KEY1_6_KEY_S 0 168 169 //***************************************************************************** 170 // 171 // The following are defines for the bit fields in the AES_O_KEY1_7 register. 172 // 173 //***************************************************************************** 174 #define AES_KEY1_7_KEY_M 0xFFFFFFFF // Key Data 175 #define AES_KEY1_7_KEY_S 0 176 177 //***************************************************************************** 178 // 179 // The following are defines for the bit fields in the AES_O_KEY1_4 register. 180 // 181 //***************************************************************************** 182 #define AES_KEY1_4_KEY_M 0xFFFFFFFF // Key Data 183 #define AES_KEY1_4_KEY_S 0 184 185 //***************************************************************************** 186 // 187 // The following are defines for the bit fields in the AES_O_KEY1_5 register. 188 // 189 //***************************************************************************** 190 #define AES_KEY1_5_KEY_M 0xFFFFFFFF // Key Data 191 #define AES_KEY1_5_KEY_S 0 192 193 //***************************************************************************** 194 // 195 // The following are defines for the bit fields in the AES_O_KEY1_2 register. 196 // 197 //***************************************************************************** 198 #define AES_KEY1_2_KEY_M 0xFFFFFFFF // Key Data 199 #define AES_KEY1_2_KEY_S 0 200 201 //***************************************************************************** 202 // 203 // The following are defines for the bit fields in the AES_O_KEY1_3 register. 204 // 205 //***************************************************************************** 206 #define AES_KEY1_3_KEY_M 0xFFFFFFFF // Key Data 207 #define AES_KEY1_3_KEY_S 0 208 209 //***************************************************************************** 210 // 211 // The following are defines for the bit fields in the AES_O_KEY1_0 register. 212 // 213 //***************************************************************************** 214 #define AES_KEY1_0_KEY_M 0xFFFFFFFF // Key Data 215 #define AES_KEY1_0_KEY_S 0 216 217 //***************************************************************************** 218 // 219 // The following are defines for the bit fields in the AES_O_KEY1_1 register. 220 // 221 //***************************************************************************** 222 #define AES_KEY1_1_KEY_M 0xFFFFFFFF // Key Data 223 #define AES_KEY1_1_KEY_S 0 224 225 //***************************************************************************** 226 // 227 // The following are defines for the bit fields in the AES_O_IV_IN_0 register. 228 // 229 //***************************************************************************** 230 #define AES_IV_IN_0_DATA_M 0xFFFFFFFF // Initialization Vector Input 231 #define AES_IV_IN_0_DATA_S 0 232 233 //***************************************************************************** 234 // 235 // The following are defines for the bit fields in the AES_O_IV_IN_1 register. 236 // 237 //***************************************************************************** 238 #define AES_IV_IN_1_DATA_M 0xFFFFFFFF // Initialization Vector Input 239 #define AES_IV_IN_1_DATA_S 0 240 241 //***************************************************************************** 242 // 243 // The following are defines for the bit fields in the AES_O_IV_IN_2 register. 244 // 245 //***************************************************************************** 246 #define AES_IV_IN_2_DATA_M 0xFFFFFFFF // Initialization Vector Input 247 #define AES_IV_IN_2_DATA_S 0 248 249 //***************************************************************************** 250 // 251 // The following are defines for the bit fields in the AES_O_IV_IN_3 register. 252 // 253 //***************************************************************************** 254 #define AES_IV_IN_3_DATA_M 0xFFFFFFFF // Initialization Vector Input 255 #define AES_IV_IN_3_DATA_S 0 256 257 //***************************************************************************** 258 // 259 // The following are defines for the bit fields in the AES_O_CTRL register. 260 // 261 //***************************************************************************** 262 #define AES_CTRL_CTXTRDY 0x80000000 // Context Data Registers Ready 263 #define AES_CTRL_SVCTXTRDY 0x40000000 // AES TAG/IV Block(s) Ready 264 #define AES_CTRL_SAVE_CONTEXT 0x20000000 // TAG or Result IV Save 265 #define AES_CTRL_CCM_M_M 0x01C00000 // Counter with CBC-MAC (CCM) 266 #define AES_CTRL_CCM_L_M 0x00380000 // L Value 267 #define AES_CTRL_CCM_L_2 0x00080000 // width = 2 268 #define AES_CTRL_CCM_L_4 0x00180000 // width = 4 269 #define AES_CTRL_CCM_L_8 0x00380000 // width = 8 270 #define AES_CTRL_CCM 0x00040000 // AES-CCM Mode Enable 271 #define AES_CTRL_GCM_M 0x00030000 // AES-GCM Mode Enable 272 #define AES_CTRL_GCM_NOP 0x00000000 // No operation 273 #define AES_CTRL_GCM_HLY0ZERO 0x00010000 // GHASH with H loaded and 274 // Y0-encrypted forced to zero 275 #define AES_CTRL_GCM_HLY0CALC 0x00020000 // GHASH with H loaded and 276 // Y0-encrypted calculated 277 // internally 278 #define AES_CTRL_GCM_HY0CALC 0x00030000 // Autonomous GHASH (both H and 279 // Y0-encrypted calculated 280 // internally) 281 #define AES_CTRL_CBCMAC 0x00008000 // AES-CBC MAC Enable 282 #define AES_CTRL_F9 0x00004000 // AES f9 Mode Enable 283 #define AES_CTRL_F8 0x00002000 // AES f8 Mode Enable 284 #define AES_CTRL_XTS_M 0x00001800 // AES-XTS Operation Enabled 285 #define AES_CTRL_XTS_NOP 0x00000000 // No operation 286 #define AES_CTRL_XTS_TWEAKJL 0x00000800 // Previous/intermediate tweak 287 // value and j loaded (value is 288 // loaded via IV, j is loaded via 289 // the AAD length register) 290 #define AES_CTRL_XTS_K2IJL 0x00001000 // Key2, n and j are loaded (n is 291 // loaded via IV, j is loaded via 292 // the AAD length register) 293 #define AES_CTRL_XTS_K2ILJ0 0x00001800 // Key2 and n are loaded; j=0 (n is 294 // loaded via IV) 295 #define AES_CTRL_CFB 0x00000400 // Full block AES cipher feedback 296 // mode (CFB128) Enable 297 #define AES_CTRL_ICM 0x00000200 // AES Integer Counter Mode (ICM) 298 // Enable 299 #define AES_CTRL_CTR_WIDTH_M 0x00000180 // AES-CTR Mode Counter Width 300 #define AES_CTRL_CTR_WIDTH_32 0x00000000 // Counter is 32 bits 301 #define AES_CTRL_CTR_WIDTH_64 0x00000080 // Counter is 64 bits 302 #define AES_CTRL_CTR_WIDTH_96 0x00000100 // Counter is 96 bits 303 #define AES_CTRL_CTR_WIDTH_128 0x00000180 // Counter is 128 bits 304 #define AES_CTRL_CTR 0x00000040 // Counter Mode 305 #define AES_CTRL_MODE 0x00000020 // ECB/CBC Mode 306 #define AES_CTRL_KEY_SIZE_M 0x00000018 // Key Size 307 #define AES_CTRL_KEY_SIZE_128 0x00000008 // Key is 128 bits 308 #define AES_CTRL_KEY_SIZE_192 0x00000010 // Key is 192 bits 309 #define AES_CTRL_KEY_SIZE_256 0x00000018 // Key is 256 bits 310 #define AES_CTRL_DIRECTION 0x00000004 // Encryption/Decryption Selection 311 #define AES_CTRL_INPUT_READY 0x00000002 // Input Ready Status 312 #define AES_CTRL_OUTPUT_READY 0x00000001 // Output Ready Status 313 #define AES_CTRL_CCM_M_S 22 314 315 //***************************************************************************** 316 // 317 // The following are defines for the bit fields in the AES_O_C_LENGTH_0 318 // register. 319 // 320 //***************************************************************************** 321 #define AES_C_LENGTH_0_LENGTH_M 0xFFFFFFFF // Data Length 322 #define AES_C_LENGTH_0_LENGTH_S 0 323 324 //***************************************************************************** 325 // 326 // The following are defines for the bit fields in the AES_O_C_LENGTH_1 327 // register. 328 // 329 //***************************************************************************** 330 #define AES_C_LENGTH_1_LENGTH_M 0xFFFFFFFF // Data Length 331 #define AES_C_LENGTH_1_LENGTH_S 0 332 333 //***************************************************************************** 334 // 335 // The following are defines for the bit fields in the AES_O_AUTH_LENGTH 336 // register. 337 // 338 //***************************************************************************** 339 #define AES_AUTH_LENGTH_AUTH_M 0xFFFFFFFF // Authentication Data Length 340 #define AES_AUTH_LENGTH_AUTH_S 0 341 342 //***************************************************************************** 343 // 344 // The following are defines for the bit fields in the AES_O_DATA_IN_0 345 // register. 346 // 347 //***************************************************************************** 348 #define AES_DATA_IN_0_DATA_M 0xFFFFFFFF // Secure Data RW 349 // Plaintext/Ciphertext 350 #define AES_DATA_IN_0_DATA_S 0 351 352 //***************************************************************************** 353 // 354 // The following are defines for the bit fields in the AES_O_DATA_IN_1 355 // register. 356 // 357 //***************************************************************************** 358 #define AES_DATA_IN_1_DATA_M 0xFFFFFFFF // Secure Data RW 359 // Plaintext/Ciphertext 360 #define AES_DATA_IN_1_DATA_S 0 361 362 //***************************************************************************** 363 // 364 // The following are defines for the bit fields in the AES_O_DATA_IN_2 365 // register. 366 // 367 //***************************************************************************** 368 #define AES_DATA_IN_2_DATA_M 0xFFFFFFFF // Secure Data RW 369 // Plaintext/Ciphertext 370 #define AES_DATA_IN_2_DATA_S 0 371 372 //***************************************************************************** 373 // 374 // The following are defines for the bit fields in the AES_O_DATA_IN_3 375 // register. 376 // 377 //***************************************************************************** 378 #define AES_DATA_IN_3_DATA_M 0xFFFFFFFF // Secure Data RW 379 // Plaintext/Ciphertext 380 #define AES_DATA_IN_3_DATA_S 0 381 382 //***************************************************************************** 383 // 384 // The following are defines for the bit fields in the AES_O_TAG_OUT_0 385 // register. 386 // 387 //***************************************************************************** 388 #define AES_TAG_OUT_0_HASH_M 0xFFFFFFFF // Hash Result 389 #define AES_TAG_OUT_0_HASH_S 0 390 391 //***************************************************************************** 392 // 393 // The following are defines for the bit fields in the AES_O_TAG_OUT_1 394 // register. 395 // 396 //***************************************************************************** 397 #define AES_TAG_OUT_1_HASH_M 0xFFFFFFFF // Hash Result 398 #define AES_TAG_OUT_1_HASH_S 0 399 400 //***************************************************************************** 401 // 402 // The following are defines for the bit fields in the AES_O_TAG_OUT_2 403 // register. 404 // 405 //***************************************************************************** 406 #define AES_TAG_OUT_2_HASH_M 0xFFFFFFFF // Hash Result 407 #define AES_TAG_OUT_2_HASH_S 0 408 409 //***************************************************************************** 410 // 411 // The following are defines for the bit fields in the AES_O_TAG_OUT_3 412 // register. 413 // 414 //***************************************************************************** 415 #define AES_TAG_OUT_3_HASH_M 0xFFFFFFFF // Hash Result 416 #define AES_TAG_OUT_3_HASH_S 0 417 418 //***************************************************************************** 419 // 420 // The following are defines for the bit fields in the AES_O_REVISION register. 421 // 422 //***************************************************************************** 423 #define AES_REVISION_M 0xFFFFFFFF // Revision number 424 #define AES_REVISION_S 0 425 426 //***************************************************************************** 427 // 428 // The following are defines for the bit fields in the AES_O_SYSCONFIG 429 // register. 430 // 431 //***************************************************************************** 432 #define AES_SYSCONFIG_K3 0x00001000 // K3 Select 433 #define AES_SYSCONFIG_KEYENC 0x00000800 // Key Encoding 434 #define AES_SYSCONFIG_MAP_CONTEXT_OUT_ON_DATA_OUT \ 435 0x00000200 // Map Context Out on Data Out 436 // Enable 437 #define AES_SYSCONFIG_DMA_REQ_CONTEXT_OUT_EN \ 438 0x00000100 // DMA Request Context Out Enable 439 #define AES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN \ 440 0x00000080 // DMA Request Context In Enable 441 #define AES_SYSCONFIG_DMA_REQ_DATA_OUT_EN \ 442 0x00000040 // DMA Request Data Out Enable 443 #define AES_SYSCONFIG_DMA_REQ_DATA_IN_EN \ 444 0x00000020 // DMA Request Data In Enable 445 #define AES_SYSCONFIG_SOFTRESET 0x00000002 // Soft reset 446 447 //***************************************************************************** 448 // 449 // The following are defines for the bit fields in the AES_O_SYSSTATUS 450 // register. 451 // 452 //***************************************************************************** 453 #define AES_SYSSTATUS_RESETDONE 0x00000001 // Reset Done 454 455 //***************************************************************************** 456 // 457 // The following are defines for the bit fields in the AES_O_IRQSTATUS 458 // register. 459 // 460 //***************************************************************************** 461 #define AES_IRQSTATUS_CONTEXT_OUT \ 462 0x00000008 // Context Output Interrupt Status 463 #define AES_IRQSTATUS_DATA_OUT 0x00000004 // Data Out Interrupt Status 464 #define AES_IRQSTATUS_DATA_IN 0x00000002 // Data In Interrupt Status 465 #define AES_IRQSTATUS_CONTEXT_IN \ 466 0x00000001 // Context In Interrupt Status 467 468 //***************************************************************************** 469 // 470 // The following are defines for the bit fields in the AES_O_IRQENABLE 471 // register. 472 // 473 //***************************************************************************** 474 #define AES_IRQENABLE_CONTEXT_OUT \ 475 0x00000008 // Context Out Interrupt Enable 476 #define AES_IRQENABLE_DATA_OUT 0x00000004 // Data Out Interrupt Enable 477 #define AES_IRQENABLE_DATA_IN 0x00000002 // Data In Interrupt Enable 478 #define AES_IRQENABLE_CONTEXT_IN \ 479 0x00000001 // Context In Interrupt Enable 480 481 //***************************************************************************** 482 // 483 // The following are defines for the bit fields in the AES_O_DIRTYBITS 484 // register. 485 // 486 //***************************************************************************** 487 #define AES_DIRTYBITS_S_DIRTY 0x00000002 // AES Dirty Bit 488 #define AES_DIRTYBITS_S_ACCESS 0x00000001 // AES Access Bit 489 490 //***************************************************************************** 491 // 492 // The following are defines for the bit fields in the AES_O_DMAIM register. 493 // 494 //***************************************************************************** 495 #define AES_DMAIM_DOUT 0x00000008 // Data Out DMA Done Interrupt Mask 496 #define AES_DMAIM_DIN 0x00000004 // Data In DMA Done Interrupt Mask 497 #define AES_DMAIM_COUT 0x00000002 // Context Out DMA Done Interrupt 498 // Mask 499 #define AES_DMAIM_CIN 0x00000001 // Context In DMA Done Interrupt 500 // Mask 501 502 //***************************************************************************** 503 // 504 // The following are defines for the bit fields in the AES_O_DMARIS register. 505 // 506 //***************************************************************************** 507 #define AES_DMARIS_DOUT 0x00000008 // Data Out DMA Done Raw Interrupt 508 // Status 509 #define AES_DMARIS_DIN 0x00000004 // Data In DMA Done Raw Interrupt 510 // Status 511 #define AES_DMARIS_COUT 0x00000002 // Context Out DMA Done Raw 512 // Interrupt Status 513 #define AES_DMARIS_CIN 0x00000001 // Context In DMA Done Raw 514 // Interrupt Status 515 516 //***************************************************************************** 517 // 518 // The following are defines for the bit fields in the AES_O_DMAMIS register. 519 // 520 //***************************************************************************** 521 #define AES_DMAMIS_DOUT 0x00000008 // Data Out DMA Done Masked 522 // Interrupt Status 523 #define AES_DMAMIS_DIN 0x00000004 // Data In DMA Done Masked 524 // Interrupt Status 525 #define AES_DMAMIS_COUT 0x00000002 // Context Out DMA Done Masked 526 // Interrupt Status 527 #define AES_DMAMIS_CIN 0x00000001 // Context In DMA Done Raw 528 // Interrupt Status 529 530 //***************************************************************************** 531 // 532 // The following are defines for the bit fields in the AES_O_DMAIC register. 533 // 534 //***************************************************************************** 535 #define AES_DMAIC_DOUT 0x00000008 // Data Out DMA Done Interrupt 536 // Clear 537 #define AES_DMAIC_DIN 0x00000004 // Data In DMA Done Interrupt Clear 538 #define AES_DMAIC_COUT 0x00000002 // Context Out DMA Done Masked 539 // Interrupt Status 540 #define AES_DMAIC_CIN 0x00000001 // Context In DMA Done Raw 541 // Interrupt Status 542 543 #endif // __HW_AES_H__ 544