1 //***************************************************************************** 2 // 3 // hw_can.h - Defines and macros used when accessing the CAN controllers. 4 // 5 // Copyright (c) 2006-2017 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Redistribution and use in source and binary forms, with or without 9 // modification, are permitted provided that the following conditions 10 // are met: 11 // 12 // Redistributions of source code must retain the above copyright 13 // notice, this list of conditions and the following disclaimer. 14 // 15 // Redistributions in binary form must reproduce the above copyright 16 // notice, this list of conditions and the following disclaimer in the 17 // documentation and/or other materials provided with the 18 // distribution. 19 // 20 // Neither the name of Texas Instruments Incorporated nor the names of 21 // its contributors may be used to endorse or promote products derived 22 // from this software without specific prior written permission. 23 // 24 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 // 36 //***************************************************************************** 37 38 #ifndef __HW_CAN_H__ 39 #define __HW_CAN_H__ 40 41 //***************************************************************************** 42 // 43 // The following are defines for the CAN register offsets. 44 // 45 //***************************************************************************** 46 #define CAN_O_CTL 0x00000000 // CAN Control 47 #define CAN_O_STS 0x00000004 // CAN Status 48 #define CAN_O_ERR 0x00000008 // CAN Error Counter 49 #define CAN_O_BIT 0x0000000C // CAN Bit Timing 50 #define CAN_O_INT 0x00000010 // CAN Interrupt 51 #define CAN_O_TST 0x00000014 // CAN Test 52 #define CAN_O_BRPE 0x00000018 // CAN Baud Rate Prescaler 53 // Extension 54 #define CAN_O_IF1CRQ 0x00000020 // CAN IF1 Command Request 55 #define CAN_O_IF1CMSK 0x00000024 // CAN IF1 Command Mask 56 #define CAN_O_IF1MSK1 0x00000028 // CAN IF1 Mask 1 57 #define CAN_O_IF1MSK2 0x0000002C // CAN IF1 Mask 2 58 #define CAN_O_IF1ARB1 0x00000030 // CAN IF1 Arbitration 1 59 #define CAN_O_IF1ARB2 0x00000034 // CAN IF1 Arbitration 2 60 #define CAN_O_IF1MCTL 0x00000038 // CAN IF1 Message Control 61 #define CAN_O_IF1DA1 0x0000003C // CAN IF1 Data A1 62 #define CAN_O_IF1DA2 0x00000040 // CAN IF1 Data A2 63 #define CAN_O_IF1DB1 0x00000044 // CAN IF1 Data B1 64 #define CAN_O_IF1DB2 0x00000048 // CAN IF1 Data B2 65 #define CAN_O_IF2CRQ 0x00000080 // CAN IF2 Command Request 66 #define CAN_O_IF2CMSK 0x00000084 // CAN IF2 Command Mask 67 #define CAN_O_IF2MSK1 0x00000088 // CAN IF2 Mask 1 68 #define CAN_O_IF2MSK2 0x0000008C // CAN IF2 Mask 2 69 #define CAN_O_IF2ARB1 0x00000090 // CAN IF2 Arbitration 1 70 #define CAN_O_IF2ARB2 0x00000094 // CAN IF2 Arbitration 2 71 #define CAN_O_IF2MCTL 0x00000098 // CAN IF2 Message Control 72 #define CAN_O_IF2DA1 0x0000009C // CAN IF2 Data A1 73 #define CAN_O_IF2DA2 0x000000A0 // CAN IF2 Data A2 74 #define CAN_O_IF2DB1 0x000000A4 // CAN IF2 Data B1 75 #define CAN_O_IF2DB2 0x000000A8 // CAN IF2 Data B2 76 #define CAN_O_TXRQ1 0x00000100 // CAN Transmission Request 1 77 #define CAN_O_TXRQ2 0x00000104 // CAN Transmission Request 2 78 #define CAN_O_NWDA1 0x00000120 // CAN New Data 1 79 #define CAN_O_NWDA2 0x00000124 // CAN New Data 2 80 #define CAN_O_MSG1INT 0x00000140 // CAN Message 1 Interrupt Pending 81 #define CAN_O_MSG2INT 0x00000144 // CAN Message 2 Interrupt Pending 82 #define CAN_O_MSG1VAL 0x00000160 // CAN Message 1 Valid 83 #define CAN_O_MSG2VAL 0x00000164 // CAN Message 2 Valid 84 85 //***************************************************************************** 86 // 87 // The following are defines for the bit fields in the CAN_O_CTL register. 88 // 89 //***************************************************************************** 90 #define CAN_CTL_TEST 0x00000080 // Test Mode Enable 91 #define CAN_CTL_CCE 0x00000040 // Configuration Change Enable 92 #define CAN_CTL_DAR 0x00000020 // Disable Automatic-Retransmission 93 #define CAN_CTL_EIE 0x00000008 // Error Interrupt Enable 94 #define CAN_CTL_SIE 0x00000004 // Status Interrupt Enable 95 #define CAN_CTL_IE 0x00000002 // CAN Interrupt Enable 96 #define CAN_CTL_INIT 0x00000001 // Initialization 97 98 //***************************************************************************** 99 // 100 // The following are defines for the bit fields in the CAN_O_STS register. 101 // 102 //***************************************************************************** 103 #define CAN_STS_BOFF 0x00000080 // Bus-Off Status 104 #define CAN_STS_EWARN 0x00000040 // Warning Status 105 #define CAN_STS_EPASS 0x00000020 // Error Passive 106 #define CAN_STS_RXOK 0x00000010 // Received a Message Successfully 107 #define CAN_STS_TXOK 0x00000008 // Transmitted a Message 108 // Successfully 109 #define CAN_STS_LEC_M 0x00000007 // Last Error Code 110 #define CAN_STS_LEC_NONE 0x00000000 // No Error 111 #define CAN_STS_LEC_STUFF 0x00000001 // Stuff Error 112 #define CAN_STS_LEC_FORM 0x00000002 // Format Error 113 #define CAN_STS_LEC_ACK 0x00000003 // ACK Error 114 #define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 Error 115 #define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 Error 116 #define CAN_STS_LEC_CRC 0x00000006 // CRC Error 117 #define CAN_STS_LEC_NOEVENT 0x00000007 // No Event 118 119 //***************************************************************************** 120 // 121 // The following are defines for the bit fields in the CAN_O_ERR register. 122 // 123 //***************************************************************************** 124 #define CAN_ERR_RP 0x00008000 // Received Error Passive 125 #define CAN_ERR_REC_M 0x00007F00 // Receive Error Counter 126 #define CAN_ERR_TEC_M 0x000000FF // Transmit Error Counter 127 #define CAN_ERR_REC_S 8 128 #define CAN_ERR_TEC_S 0 129 130 //***************************************************************************** 131 // 132 // The following are defines for the bit fields in the CAN_O_BIT register. 133 // 134 //***************************************************************************** 135 #define CAN_BIT_TSEG2_M 0x00007000 // Time Segment after Sample Point 136 #define CAN_BIT_TSEG1_M 0x00000F00 // Time Segment Before Sample Point 137 #define CAN_BIT_SJW_M 0x000000C0 // (Re)Synchronization Jump Width 138 #define CAN_BIT_BRP_M 0x0000003F // Baud Rate Prescaler 139 #define CAN_BIT_TSEG2_S 12 140 #define CAN_BIT_TSEG1_S 8 141 #define CAN_BIT_SJW_S 6 142 #define CAN_BIT_BRP_S 0 143 144 //***************************************************************************** 145 // 146 // The following are defines for the bit fields in the CAN_O_INT register. 147 // 148 //***************************************************************************** 149 #define CAN_INT_INTID_M 0x0000FFFF // Interrupt Identifier 150 #define CAN_INT_INTID_NONE 0x00000000 // No interrupt pending 151 #define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt 152 153 //***************************************************************************** 154 // 155 // The following are defines for the bit fields in the CAN_O_TST register. 156 // 157 //***************************************************************************** 158 #define CAN_TST_RX 0x00000080 // Receive Observation 159 #define CAN_TST_TX_M 0x00000060 // Transmit Control 160 #define CAN_TST_TX_CANCTL 0x00000000 // CAN Module Control 161 #define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point 162 #define CAN_TST_TX_DOMINANT 0x00000040 // Driven Low 163 #define CAN_TST_TX_RECESSIVE 0x00000060 // Driven High 164 #define CAN_TST_LBACK 0x00000010 // Loopback Mode 165 #define CAN_TST_SILENT 0x00000008 // Silent Mode 166 #define CAN_TST_BASIC 0x00000004 // Basic Mode 167 168 //***************************************************************************** 169 // 170 // The following are defines for the bit fields in the CAN_O_BRPE register. 171 // 172 //***************************************************************************** 173 #define CAN_BRPE_BRPE_M 0x0000000F // Baud Rate Prescaler Extension 174 #define CAN_BRPE_BRPE_S 0 175 176 //***************************************************************************** 177 // 178 // The following are defines for the bit fields in the CAN_O_IF1CRQ register. 179 // 180 //***************************************************************************** 181 #define CAN_IF1CRQ_BUSY 0x00008000 // Busy Flag 182 #define CAN_IF1CRQ_MNUM_M 0x0000003F // Message Number 183 #define CAN_IF1CRQ_MNUM_S 0 184 185 //***************************************************************************** 186 // 187 // The following are defines for the bit fields in the CAN_O_IF1CMSK register. 188 // 189 //***************************************************************************** 190 #define CAN_IF1CMSK_WRNRD 0x00000080 // Write, Not Read 191 #define CAN_IF1CMSK_MASK 0x00000040 // Access Mask Bits 192 #define CAN_IF1CMSK_ARB 0x00000020 // Access Arbitration Bits 193 #define CAN_IF1CMSK_CONTROL 0x00000010 // Access Control Bits 194 #define CAN_IF1CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit 195 #define CAN_IF1CMSK_NEWDAT 0x00000004 // Access New Data 196 #define CAN_IF1CMSK_TXRQST 0x00000004 // Access Transmission Request 197 #define CAN_IF1CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3 198 #define CAN_IF1CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7 199 200 //***************************************************************************** 201 // 202 // The following are defines for the bit fields in the CAN_O_IF1MSK1 register. 203 // 204 //***************************************************************************** 205 #define CAN_IF1MSK1_IDMSK_M 0x0000FFFF // Identifier Mask 206 #define CAN_IF1MSK1_IDMSK_S 0 207 208 //***************************************************************************** 209 // 210 // The following are defines for the bit fields in the CAN_O_IF1MSK2 register. 211 // 212 //***************************************************************************** 213 #define CAN_IF1MSK2_MXTD 0x00008000 // Mask Extended Identifier 214 #define CAN_IF1MSK2_MDIR 0x00004000 // Mask Message Direction 215 #define CAN_IF1MSK2_IDMSK_M 0x00001FFF // Identifier Mask 216 #define CAN_IF1MSK2_IDMSK_S 0 217 218 //***************************************************************************** 219 // 220 // The following are defines for the bit fields in the CAN_O_IF1ARB1 register. 221 // 222 //***************************************************************************** 223 #define CAN_IF1ARB1_ID_M 0x0000FFFF // Message Identifier 224 #define CAN_IF1ARB1_ID_S 0 225 226 //***************************************************************************** 227 // 228 // The following are defines for the bit fields in the CAN_O_IF1ARB2 register. 229 // 230 //***************************************************************************** 231 #define CAN_IF1ARB2_MSGVAL 0x00008000 // Message Valid 232 #define CAN_IF1ARB2_XTD 0x00004000 // Extended Identifier 233 #define CAN_IF1ARB2_DIR 0x00002000 // Message Direction 234 #define CAN_IF1ARB2_ID_M 0x00001FFF // Message Identifier 235 #define CAN_IF1ARB2_ID_S 0 236 237 //***************************************************************************** 238 // 239 // The following are defines for the bit fields in the CAN_O_IF1MCTL register. 240 // 241 //***************************************************************************** 242 #define CAN_IF1MCTL_NEWDAT 0x00008000 // New Data 243 #define CAN_IF1MCTL_MSGLST 0x00004000 // Message Lost 244 #define CAN_IF1MCTL_INTPND 0x00002000 // Interrupt Pending 245 #define CAN_IF1MCTL_UMASK 0x00001000 // Use Acceptance Mask 246 #define CAN_IF1MCTL_TXIE 0x00000800 // Transmit Interrupt Enable 247 #define CAN_IF1MCTL_RXIE 0x00000400 // Receive Interrupt Enable 248 #define CAN_IF1MCTL_RMTEN 0x00000200 // Remote Enable 249 #define CAN_IF1MCTL_TXRQST 0x00000100 // Transmit Request 250 #define CAN_IF1MCTL_EOB 0x00000080 // End of Buffer 251 #define CAN_IF1MCTL_DLC_M 0x0000000F // Data Length Code 252 #define CAN_IF1MCTL_DLC_S 0 253 254 //***************************************************************************** 255 // 256 // The following are defines for the bit fields in the CAN_O_IF1DA1 register. 257 // 258 //***************************************************************************** 259 #define CAN_IF1DA1_DATA_M 0x0000FFFF // Data 260 #define CAN_IF1DA1_DATA_S 0 261 262 //***************************************************************************** 263 // 264 // The following are defines for the bit fields in the CAN_O_IF1DA2 register. 265 // 266 //***************************************************************************** 267 #define CAN_IF1DA2_DATA_M 0x0000FFFF // Data 268 #define CAN_IF1DA2_DATA_S 0 269 270 //***************************************************************************** 271 // 272 // The following are defines for the bit fields in the CAN_O_IF1DB1 register. 273 // 274 //***************************************************************************** 275 #define CAN_IF1DB1_DATA_M 0x0000FFFF // Data 276 #define CAN_IF1DB1_DATA_S 0 277 278 //***************************************************************************** 279 // 280 // The following are defines for the bit fields in the CAN_O_IF1DB2 register. 281 // 282 //***************************************************************************** 283 #define CAN_IF1DB2_DATA_M 0x0000FFFF // Data 284 #define CAN_IF1DB2_DATA_S 0 285 286 //***************************************************************************** 287 // 288 // The following are defines for the bit fields in the CAN_O_IF2CRQ register. 289 // 290 //***************************************************************************** 291 #define CAN_IF2CRQ_BUSY 0x00008000 // Busy Flag 292 #define CAN_IF2CRQ_MNUM_M 0x0000003F // Message Number 293 #define CAN_IF2CRQ_MNUM_S 0 294 295 //***************************************************************************** 296 // 297 // The following are defines for the bit fields in the CAN_O_IF2CMSK register. 298 // 299 //***************************************************************************** 300 #define CAN_IF2CMSK_WRNRD 0x00000080 // Write, Not Read 301 #define CAN_IF2CMSK_MASK 0x00000040 // Access Mask Bits 302 #define CAN_IF2CMSK_ARB 0x00000020 // Access Arbitration Bits 303 #define CAN_IF2CMSK_CONTROL 0x00000010 // Access Control Bits 304 #define CAN_IF2CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit 305 #define CAN_IF2CMSK_NEWDAT 0x00000004 // Access New Data 306 #define CAN_IF2CMSK_TXRQST 0x00000004 // Access Transmission Request 307 #define CAN_IF2CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3 308 #define CAN_IF2CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7 309 310 //***************************************************************************** 311 // 312 // The following are defines for the bit fields in the CAN_O_IF2MSK1 register. 313 // 314 //***************************************************************************** 315 #define CAN_IF2MSK1_IDMSK_M 0x0000FFFF // Identifier Mask 316 #define CAN_IF2MSK1_IDMSK_S 0 317 318 //***************************************************************************** 319 // 320 // The following are defines for the bit fields in the CAN_O_IF2MSK2 register. 321 // 322 //***************************************************************************** 323 #define CAN_IF2MSK2_MXTD 0x00008000 // Mask Extended Identifier 324 #define CAN_IF2MSK2_MDIR 0x00004000 // Mask Message Direction 325 #define CAN_IF2MSK2_IDMSK_M 0x00001FFF // Identifier Mask 326 #define CAN_IF2MSK2_IDMSK_S 0 327 328 //***************************************************************************** 329 // 330 // The following are defines for the bit fields in the CAN_O_IF2ARB1 register. 331 // 332 //***************************************************************************** 333 #define CAN_IF2ARB1_ID_M 0x0000FFFF // Message Identifier 334 #define CAN_IF2ARB1_ID_S 0 335 336 //***************************************************************************** 337 // 338 // The following are defines for the bit fields in the CAN_O_IF2ARB2 register. 339 // 340 //***************************************************************************** 341 #define CAN_IF2ARB2_MSGVAL 0x00008000 // Message Valid 342 #define CAN_IF2ARB2_XTD 0x00004000 // Extended Identifier 343 #define CAN_IF2ARB2_DIR 0x00002000 // Message Direction 344 #define CAN_IF2ARB2_ID_M 0x00001FFF // Message Identifier 345 #define CAN_IF2ARB2_ID_S 0 346 347 //***************************************************************************** 348 // 349 // The following are defines for the bit fields in the CAN_O_IF2MCTL register. 350 // 351 //***************************************************************************** 352 #define CAN_IF2MCTL_NEWDAT 0x00008000 // New Data 353 #define CAN_IF2MCTL_MSGLST 0x00004000 // Message Lost 354 #define CAN_IF2MCTL_INTPND 0x00002000 // Interrupt Pending 355 #define CAN_IF2MCTL_UMASK 0x00001000 // Use Acceptance Mask 356 #define CAN_IF2MCTL_TXIE 0x00000800 // Transmit Interrupt Enable 357 #define CAN_IF2MCTL_RXIE 0x00000400 // Receive Interrupt Enable 358 #define CAN_IF2MCTL_RMTEN 0x00000200 // Remote Enable 359 #define CAN_IF2MCTL_TXRQST 0x00000100 // Transmit Request 360 #define CAN_IF2MCTL_EOB 0x00000080 // End of Buffer 361 #define CAN_IF2MCTL_DLC_M 0x0000000F // Data Length Code 362 #define CAN_IF2MCTL_DLC_S 0 363 364 //***************************************************************************** 365 // 366 // The following are defines for the bit fields in the CAN_O_IF2DA1 register. 367 // 368 //***************************************************************************** 369 #define CAN_IF2DA1_DATA_M 0x0000FFFF // Data 370 #define CAN_IF2DA1_DATA_S 0 371 372 //***************************************************************************** 373 // 374 // The following are defines for the bit fields in the CAN_O_IF2DA2 register. 375 // 376 //***************************************************************************** 377 #define CAN_IF2DA2_DATA_M 0x0000FFFF // Data 378 #define CAN_IF2DA2_DATA_S 0 379 380 //***************************************************************************** 381 // 382 // The following are defines for the bit fields in the CAN_O_IF2DB1 register. 383 // 384 //***************************************************************************** 385 #define CAN_IF2DB1_DATA_M 0x0000FFFF // Data 386 #define CAN_IF2DB1_DATA_S 0 387 388 //***************************************************************************** 389 // 390 // The following are defines for the bit fields in the CAN_O_IF2DB2 register. 391 // 392 //***************************************************************************** 393 #define CAN_IF2DB2_DATA_M 0x0000FFFF // Data 394 #define CAN_IF2DB2_DATA_S 0 395 396 //***************************************************************************** 397 // 398 // The following are defines for the bit fields in the CAN_O_TXRQ1 register. 399 // 400 //***************************************************************************** 401 #define CAN_TXRQ1_TXRQST_M 0x0000FFFF // Transmission Request Bits 402 #define CAN_TXRQ1_TXRQST_S 0 403 404 //***************************************************************************** 405 // 406 // The following are defines for the bit fields in the CAN_O_TXRQ2 register. 407 // 408 //***************************************************************************** 409 #define CAN_TXRQ2_TXRQST_M 0x0000FFFF // Transmission Request Bits 410 #define CAN_TXRQ2_TXRQST_S 0 411 412 //***************************************************************************** 413 // 414 // The following are defines for the bit fields in the CAN_O_NWDA1 register. 415 // 416 //***************************************************************************** 417 #define CAN_NWDA1_NEWDAT_M 0x0000FFFF // New Data Bits 418 #define CAN_NWDA1_NEWDAT_S 0 419 420 //***************************************************************************** 421 // 422 // The following are defines for the bit fields in the CAN_O_NWDA2 register. 423 // 424 //***************************************************************************** 425 #define CAN_NWDA2_NEWDAT_M 0x0000FFFF // New Data Bits 426 #define CAN_NWDA2_NEWDAT_S 0 427 428 //***************************************************************************** 429 // 430 // The following are defines for the bit fields in the CAN_O_MSG1INT register. 431 // 432 //***************************************************************************** 433 #define CAN_MSG1INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits 434 #define CAN_MSG1INT_INTPND_S 0 435 436 //***************************************************************************** 437 // 438 // The following are defines for the bit fields in the CAN_O_MSG2INT register. 439 // 440 //***************************************************************************** 441 #define CAN_MSG2INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits 442 #define CAN_MSG2INT_INTPND_S 0 443 444 //***************************************************************************** 445 // 446 // The following are defines for the bit fields in the CAN_O_MSG1VAL register. 447 // 448 //***************************************************************************** 449 #define CAN_MSG1VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits 450 #define CAN_MSG1VAL_MSGVAL_S 0 451 452 //***************************************************************************** 453 // 454 // The following are defines for the bit fields in the CAN_O_MSG2VAL register. 455 // 456 //***************************************************************************** 457 #define CAN_MSG2VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits 458 #define CAN_MSG2VAL_MSGVAL_S 0 459 460 #endif // __HW_CAN_H__ 461