1 //*****************************************************************************
2 //
3 // hw_qei.h - Macros used when accessing the QEI hardware.
4 //
5 // Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
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36 //*****************************************************************************
37 
38 #ifndef __HW_QEI_H__
39 #define __HW_QEI_H__
40 
41 //*****************************************************************************
42 //
43 // The following are defines for the QEI register offsets.
44 //
45 //*****************************************************************************
46 #define QEI_O_CTL               0x00000000  // QEI Control
47 #define QEI_O_STAT              0x00000004  // QEI Status
48 #define QEI_O_POS               0x00000008  // QEI Position
49 #define QEI_O_MAXPOS            0x0000000C  // QEI Maximum Position
50 #define QEI_O_LOAD              0x00000010  // QEI Timer Load
51 #define QEI_O_TIME              0x00000014  // QEI Timer
52 #define QEI_O_COUNT             0x00000018  // QEI Velocity Counter
53 #define QEI_O_SPEED             0x0000001C  // QEI Velocity
54 #define QEI_O_INTEN             0x00000020  // QEI Interrupt Enable
55 #define QEI_O_RIS               0x00000024  // QEI Raw Interrupt Status
56 #define QEI_O_ISC               0x00000028  // QEI Interrupt Status and Clear
57 
58 //*****************************************************************************
59 //
60 // The following are defines for the bit fields in the QEI_O_CTL register.
61 //
62 //*****************************************************************************
63 #define QEI_CTL_FILTCNT_M       0x000F0000  // Input Filter Prescale Count
64 #define QEI_CTL_FILTEN          0x00002000  // Enable Input Filter
65 #define QEI_CTL_STALLEN         0x00001000  // Stall QEI
66 #define QEI_CTL_INVI            0x00000800  // Invert Index Pulse
67 #define QEI_CTL_INVB            0x00000400  // Invert PhB
68 #define QEI_CTL_INVA            0x00000200  // Invert PhA
69 #define QEI_CTL_VELDIV_M        0x000001C0  // Predivide Velocity
70 #define QEI_CTL_VELDIV_1        0x00000000  // QEI clock /1
71 #define QEI_CTL_VELDIV_2        0x00000040  // QEI clock /2
72 #define QEI_CTL_VELDIV_4        0x00000080  // QEI clock /4
73 #define QEI_CTL_VELDIV_8        0x000000C0  // QEI clock /8
74 #define QEI_CTL_VELDIV_16       0x00000100  // QEI clock /16
75 #define QEI_CTL_VELDIV_32       0x00000140  // QEI clock /32
76 #define QEI_CTL_VELDIV_64       0x00000180  // QEI clock /64
77 #define QEI_CTL_VELDIV_128      0x000001C0  // QEI clock /128
78 #define QEI_CTL_VELEN           0x00000020  // Capture Velocity
79 #define QEI_CTL_RESMODE         0x00000010  // Reset Mode
80 #define QEI_CTL_CAPMODE         0x00000008  // Capture Mode
81 #define QEI_CTL_SIGMODE         0x00000004  // Signal Mode
82 #define QEI_CTL_SWAP            0x00000002  // Swap Signals
83 #define QEI_CTL_ENABLE          0x00000001  // Enable QEI
84 #define QEI_CTL_FILTCNT_S       16
85 
86 //*****************************************************************************
87 //
88 // The following are defines for the bit fields in the QEI_O_STAT register.
89 //
90 //*****************************************************************************
91 #define QEI_STAT_DIRECTION      0x00000002  // Direction of Rotation
92 #define QEI_STAT_ERROR          0x00000001  // Error Detected
93 
94 //*****************************************************************************
95 //
96 // The following are defines for the bit fields in the QEI_O_POS register.
97 //
98 //*****************************************************************************
99 #define QEI_POS_M               0xFFFFFFFF  // Current Position Integrator
100                                             // Value
101 #define QEI_POS_S               0
102 
103 //*****************************************************************************
104 //
105 // The following are defines for the bit fields in the QEI_O_MAXPOS register.
106 //
107 //*****************************************************************************
108 #define QEI_MAXPOS_M            0xFFFFFFFF  // Maximum Position Integrator
109                                             // Value
110 #define QEI_MAXPOS_S            0
111 
112 //*****************************************************************************
113 //
114 // The following are defines for the bit fields in the QEI_O_LOAD register.
115 //
116 //*****************************************************************************
117 #define QEI_LOAD_M              0xFFFFFFFF  // Velocity Timer Load Value
118 #define QEI_LOAD_S              0
119 
120 //*****************************************************************************
121 //
122 // The following are defines for the bit fields in the QEI_O_TIME register.
123 //
124 //*****************************************************************************
125 #define QEI_TIME_M              0xFFFFFFFF  // Velocity Timer Current Value
126 #define QEI_TIME_S              0
127 
128 //*****************************************************************************
129 //
130 // The following are defines for the bit fields in the QEI_O_COUNT register.
131 //
132 //*****************************************************************************
133 #define QEI_COUNT_M             0xFFFFFFFF  // Velocity Pulse Count
134 #define QEI_COUNT_S             0
135 
136 //*****************************************************************************
137 //
138 // The following are defines for the bit fields in the QEI_O_SPEED register.
139 //
140 //*****************************************************************************
141 #define QEI_SPEED_M             0xFFFFFFFF  // Velocity
142 #define QEI_SPEED_S             0
143 
144 //*****************************************************************************
145 //
146 // The following are defines for the bit fields in the QEI_O_INTEN register.
147 //
148 //*****************************************************************************
149 #define QEI_INTEN_ERROR         0x00000008  // Phase Error Interrupt Enable
150 #define QEI_INTEN_DIR           0x00000004  // Direction Change Interrupt
151                                             // Enable
152 #define QEI_INTEN_TIMER         0x00000002  // Timer Expires Interrupt Enable
153 #define QEI_INTEN_INDEX         0x00000001  // Index Pulse Detected Interrupt
154                                             // Enable
155 
156 //*****************************************************************************
157 //
158 // The following are defines for the bit fields in the QEI_O_RIS register.
159 //
160 //*****************************************************************************
161 #define QEI_RIS_ERROR           0x00000008  // Phase Error Detected
162 #define QEI_RIS_DIR             0x00000004  // Direction Change Detected
163 #define QEI_RIS_TIMER           0x00000002  // Velocity Timer Expired
164 #define QEI_RIS_INDEX           0x00000001  // Index Pulse Asserted
165 
166 //*****************************************************************************
167 //
168 // The following are defines for the bit fields in the QEI_O_ISC register.
169 //
170 //*****************************************************************************
171 #define QEI_ISC_ERROR           0x00000008  // Phase Error Interrupt
172 #define QEI_ISC_DIR             0x00000004  // Direction Change Interrupt
173 #define QEI_ISC_TIMER           0x00000002  // Velocity Timer Expired Interrupt
174 #define QEI_ISC_INDEX           0x00000001  // Index Pulse Interrupt
175 
176 #endif // __HW_QEI_H__
177