1 //***************************************************************************** 2 // 3 // hw_shamd5.h - Macros used when accessing the SHA/MD5 hardware. 4 // 5 // Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Redistribution and use in source and binary forms, with or without 9 // modification, are permitted provided that the following conditions 10 // are met: 11 // 12 // Redistributions of source code must retain the above copyright 13 // notice, this list of conditions and the following disclaimer. 14 // 15 // Redistributions in binary form must reproduce the above copyright 16 // notice, this list of conditions and the following disclaimer in the 17 // documentation and/or other materials provided with the 18 // distribution. 19 // 20 // Neither the name of Texas Instruments Incorporated nor the names of 21 // its contributors may be used to endorse or promote products derived 22 // from this software without specific prior written permission. 23 // 24 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 // 36 //***************************************************************************** 37 38 #ifndef __HW_SHAMD5_H__ 39 #define __HW_SHAMD5_H__ 40 41 //***************************************************************************** 42 // 43 // The following are defines for the SHA/MD5 register offsets. 44 // 45 //***************************************************************************** 46 #define SHAMD5_O_ODIGEST_A 0x00000000 // SHA Outer Digest A 47 #define SHAMD5_O_ODIGEST_B 0x00000004 // SHA Outer Digest B 48 #define SHAMD5_O_ODIGEST_C 0x00000008 // SHA Outer Digest C 49 #define SHAMD5_O_ODIGEST_D 0x0000000C // SHA Outer Digest D 50 #define SHAMD5_O_ODIGEST_E 0x00000010 // SHA Outer Digest E 51 #define SHAMD5_O_ODIGEST_F 0x00000014 // SHA Outer Digest F 52 #define SHAMD5_O_ODIGEST_G 0x00000018 // SHA Outer Digest G 53 #define SHAMD5_O_ODIGEST_H 0x0000001C // SHA Outer Digest H 54 #define SHAMD5_O_IDIGEST_A 0x00000020 // SHA Inner Digest A 55 #define SHAMD5_O_IDIGEST_B 0x00000024 // SHA Inner Digest B 56 #define SHAMD5_O_IDIGEST_C 0x00000028 // SHA Inner Digest C 57 #define SHAMD5_O_IDIGEST_D 0x0000002C // SHA Inner Digest D 58 #define SHAMD5_O_IDIGEST_E 0x00000030 // SHA Inner Digest E 59 #define SHAMD5_O_IDIGEST_F 0x00000034 // SHA Inner Digest F 60 #define SHAMD5_O_IDIGEST_G 0x00000038 // SHA Inner Digest G 61 #define SHAMD5_O_IDIGEST_H 0x0000003C // SHA Inner Digest H 62 #define SHAMD5_O_DIGEST_COUNT 0x00000040 // SHA Digest Count 63 #define SHAMD5_O_MODE 0x00000044 // SHA Mode 64 #define SHAMD5_O_LENGTH 0x00000048 // SHA Length 65 #define SHAMD5_O_DATA_0_IN 0x00000080 // SHA Data 0 Input 66 #define SHAMD5_O_DATA_1_IN 0x00000084 // SHA Data 1 Input 67 #define SHAMD5_O_DATA_2_IN 0x00000088 // SHA Data 2 Input 68 #define SHAMD5_O_DATA_3_IN 0x0000008C // SHA Data 3 Input 69 #define SHAMD5_O_DATA_4_IN 0x00000090 // SHA Data 4 Input 70 #define SHAMD5_O_DATA_5_IN 0x00000094 // SHA Data 5 Input 71 #define SHAMD5_O_DATA_6_IN 0x00000098 // SHA Data 6 Input 72 #define SHAMD5_O_DATA_7_IN 0x0000009C // SHA Data 7 Input 73 #define SHAMD5_O_DATA_8_IN 0x000000A0 // SHA Data 8 Input 74 #define SHAMD5_O_DATA_9_IN 0x000000A4 // SHA Data 9 Input 75 #define SHAMD5_O_DATA_10_IN 0x000000A8 // SHA Data 10 Input 76 #define SHAMD5_O_DATA_11_IN 0x000000AC // SHA Data 11 Input 77 #define SHAMD5_O_DATA_12_IN 0x000000B0 // SHA Data 12 Input 78 #define SHAMD5_O_DATA_13_IN 0x000000B4 // SHA Data 13 Input 79 #define SHAMD5_O_DATA_14_IN 0x000000B8 // SHA Data 14 Input 80 #define SHAMD5_O_DATA_15_IN 0x000000BC // SHA Data 15 Input 81 #define SHAMD5_O_REVISION 0x00000100 // SHA Revision 82 #define SHAMD5_O_SYSCONFIG 0x00000110 // SHA System Configuration 83 #define SHAMD5_O_SYSSTATUS 0x00000114 // SHA System Status 84 #define SHAMD5_O_IRQSTATUS 0x00000118 // SHA Interrupt Status 85 #define SHAMD5_O_IRQENABLE 0x0000011C // SHA Interrupt Enable 86 #define SHAMD5_O_DMAIM 0xFFFFC010 // SHA DMA Interrupt Mask 87 #define SHAMD5_O_DMARIS 0xFFFFC014 // SHA DMA Raw Interrupt Status 88 #define SHAMD5_O_DMAMIS 0xFFFFC018 // SHA DMA Masked Interrupt Status 89 #define SHAMD5_O_DMAIC 0xFFFFC01C // SHA DMA Interrupt Clear 90 91 //***************************************************************************** 92 // 93 // The following are defines for the bit fields in the SHAMD5_O_ODIGEST_A 94 // register. 95 // 96 //***************************************************************************** 97 #define SHAMD5_ODIGEST_A_DATA_M 0xFFFFFFFF // Digest/Key Data 98 #define SHAMD5_ODIGEST_A_DATA_S 0 99 100 //***************************************************************************** 101 // 102 // The following are defines for the bit fields in the SHAMD5_O_ODIGEST_B 103 // register. 104 // 105 //***************************************************************************** 106 #define SHAMD5_ODIGEST_B_DATA_M 0xFFFFFFFF // Digest/Key Data 107 #define SHAMD5_ODIGEST_B_DATA_S 0 108 109 //***************************************************************************** 110 // 111 // The following are defines for the bit fields in the SHAMD5_O_ODIGEST_C 112 // register. 113 // 114 //***************************************************************************** 115 #define SHAMD5_ODIGEST_C_DATA_M 0xFFFFFFFF // Digest/Key Data 116 #define SHAMD5_ODIGEST_C_DATA_S 0 117 118 //***************************************************************************** 119 // 120 // The following are defines for the bit fields in the SHAMD5_O_ODIGEST_D 121 // register. 122 // 123 //***************************************************************************** 124 #define SHAMD5_ODIGEST_D_DATA_M 0xFFFFFFFF // Digest/Key Data 125 #define SHAMD5_ODIGEST_D_DATA_S 0 126 127 //***************************************************************************** 128 // 129 // The following are defines for the bit fields in the SHAMD5_O_ODIGEST_E 130 // register. 131 // 132 //***************************************************************************** 133 #define SHAMD5_ODIGEST_E_DATA_M 0xFFFFFFFF // Digest/Key Data 134 #define SHAMD5_ODIGEST_E_DATA_S 0 135 136 //***************************************************************************** 137 // 138 // The following are defines for the bit fields in the SHAMD5_O_ODIGEST_F 139 // register. 140 // 141 //***************************************************************************** 142 #define SHAMD5_ODIGEST_F_DATA_M 0xFFFFFFFF // Digest/Key Data 143 #define SHAMD5_ODIGEST_F_DATA_S 0 144 145 //***************************************************************************** 146 // 147 // The following are defines for the bit fields in the SHAMD5_O_ODIGEST_G 148 // register. 149 // 150 //***************************************************************************** 151 #define SHAMD5_ODIGEST_G_DATA_M 0xFFFFFFFF // Digest/Key Data 152 #define SHAMD5_ODIGEST_G_DATA_S 0 153 154 //***************************************************************************** 155 // 156 // The following are defines for the bit fields in the SHAMD5_O_ODIGEST_H 157 // register. 158 // 159 //***************************************************************************** 160 #define SHAMD5_ODIGEST_H_DATA_M 0xFFFFFFFF // Digest/Key Data 161 #define SHAMD5_ODIGEST_H_DATA_S 0 162 163 //***************************************************************************** 164 // 165 // The following are defines for the bit fields in the SHAMD5_O_IDIGEST_A 166 // register. 167 // 168 //***************************************************************************** 169 #define SHAMD5_IDIGEST_A_DATA_M 0xFFFFFFFF // Digest/Key Data 170 #define SHAMD5_IDIGEST_A_DATA_S 0 171 172 //***************************************************************************** 173 // 174 // The following are defines for the bit fields in the SHAMD5_O_IDIGEST_B 175 // register. 176 // 177 //***************************************************************************** 178 #define SHAMD5_IDIGEST_B_DATA_M 0xFFFFFFFF // Digest/Key Data 179 #define SHAMD5_IDIGEST_B_DATA_S 0 180 181 //***************************************************************************** 182 // 183 // The following are defines for the bit fields in the SHAMD5_O_IDIGEST_C 184 // register. 185 // 186 //***************************************************************************** 187 #define SHAMD5_IDIGEST_C_DATA_M 0xFFFFFFFF // Digest/Key Data 188 #define SHAMD5_IDIGEST_C_DATA_S 0 189 190 //***************************************************************************** 191 // 192 // The following are defines for the bit fields in the SHAMD5_O_IDIGEST_D 193 // register. 194 // 195 //***************************************************************************** 196 #define SHAMD5_IDIGEST_D_DATA_M 0xFFFFFFFF // Digest/Key Data 197 #define SHAMD5_IDIGEST_D_DATA_S 0 198 199 //***************************************************************************** 200 // 201 // The following are defines for the bit fields in the SHAMD5_O_IDIGEST_E 202 // register. 203 // 204 //***************************************************************************** 205 #define SHAMD5_IDIGEST_E_DATA_M 0xFFFFFFFF // Digest/Key Data 206 #define SHAMD5_IDIGEST_E_DATA_S 0 207 208 //***************************************************************************** 209 // 210 // The following are defines for the bit fields in the SHAMD5_O_IDIGEST_F 211 // register. 212 // 213 //***************************************************************************** 214 #define SHAMD5_IDIGEST_F_DATA_M 0xFFFFFFFF // Digest/Key Data 215 #define SHAMD5_IDIGEST_F_DATA_S 0 216 217 //***************************************************************************** 218 // 219 // The following are defines for the bit fields in the SHAMD5_O_IDIGEST_G 220 // register. 221 // 222 //***************************************************************************** 223 #define SHAMD5_IDIGEST_G_DATA_M 0xFFFFFFFF // Digest/Key Data 224 #define SHAMD5_IDIGEST_G_DATA_S 0 225 226 //***************************************************************************** 227 // 228 // The following are defines for the bit fields in the SHAMD5_O_IDIGEST_H 229 // register. 230 // 231 //***************************************************************************** 232 #define SHAMD5_IDIGEST_H_DATA_M 0xFFFFFFFF // Digest/Key Data 233 #define SHAMD5_IDIGEST_H_DATA_S 0 234 235 //***************************************************************************** 236 // 237 // The following are defines for the bit fields in the SHAMD5_O_DIGEST_COUNT 238 // register. 239 // 240 //***************************************************************************** 241 #define SHAMD5_DIGEST_COUNT_M 0xFFFFFFFF // Digest Count 242 #define SHAMD5_DIGEST_COUNT_S 0 243 244 //***************************************************************************** 245 // 246 // The following are defines for the bit fields in the SHAMD5_O_MODE register. 247 // 248 //***************************************************************************** 249 #define SHAMD5_MODE_HMAC_OUTER_HASH \ 250 0x00000080 // HMAC Outer Hash Processing 251 // Enable 252 #define SHAMD5_MODE_HMAC_KEY_PROC \ 253 0x00000020 // HMAC Key Processing Enable 254 #define SHAMD5_MODE_CLOSE_HASH 0x00000010 // Performs the padding, the 255 // Hash/HMAC will be 'closed' at 256 // the end of the block, as per 257 // MD5/SHA-1/SHA-2 specification 258 #define SHAMD5_MODE_ALGO_CONSTANT \ 259 0x00000008 // The initial digest register will 260 // be overwritten with the 261 // algorithm constants for the 262 // selected algorithm when hashing 263 // and the initial digest count 264 // register will be reset to 0 265 #define SHAMD5_MODE_ALGO_M 0x00000007 // Hash Algorithm 266 #define SHAMD5_MODE_ALGO_MD5 0x00000000 // MD5 267 #define SHAMD5_MODE_ALGO_SHA1 0x00000002 // SHA-1 268 #define SHAMD5_MODE_ALGO_SHA224 0x00000004 // SHA-224 269 #define SHAMD5_MODE_ALGO_SHA256 0x00000006 // SHA-256 270 271 //***************************************************************************** 272 // 273 // The following are defines for the bit fields in the SHAMD5_O_LENGTH 274 // register. 275 // 276 //***************************************************************************** 277 #define SHAMD5_LENGTH_M 0xFFFFFFFF // Block Length/Remaining Byte 278 // Count 279 #define SHAMD5_LENGTH_S 0 280 281 //***************************************************************************** 282 // 283 // The following are defines for the bit fields in the SHAMD5_O_DATA_0_IN 284 // register. 285 // 286 //***************************************************************************** 287 #define SHAMD5_DATA_0_IN_DATA_M 0xFFFFFFFF // Digest/Key Data 288 #define SHAMD5_DATA_0_IN_DATA_S 0 289 290 //***************************************************************************** 291 // 292 // The following are defines for the bit fields in the SHAMD5_O_DATA_1_IN 293 // register. 294 // 295 //***************************************************************************** 296 #define SHAMD5_DATA_1_IN_DATA_M 0xFFFFFFFF // Digest/Key Data 297 #define SHAMD5_DATA_1_IN_DATA_S 0 298 299 //***************************************************************************** 300 // 301 // The following are defines for the bit fields in the SHAMD5_O_DATA_2_IN 302 // register. 303 // 304 //***************************************************************************** 305 #define SHAMD5_DATA_2_IN_DATA_M 0xFFFFFFFF // Digest/Key Data 306 #define SHAMD5_DATA_2_IN_DATA_S 0 307 308 //***************************************************************************** 309 // 310 // The following are defines for the bit fields in the SHAMD5_O_DATA_3_IN 311 // register. 312 // 313 //***************************************************************************** 314 #define SHAMD5_DATA_3_IN_DATA_M 0xFFFFFFFF // Digest/Key Data 315 #define SHAMD5_DATA_3_IN_DATA_S 0 316 317 //***************************************************************************** 318 // 319 // The following are defines for the bit fields in the SHAMD5_O_DATA_4_IN 320 // register. 321 // 322 //***************************************************************************** 323 #define SHAMD5_DATA_4_IN_DATA_M 0xFFFFFFFF // Digest/Key Data 324 #define SHAMD5_DATA_4_IN_DATA_S 0 325 326 //***************************************************************************** 327 // 328 // The following are defines for the bit fields in the SHAMD5_O_DATA_5_IN 329 // register. 330 // 331 //***************************************************************************** 332 #define SHAMD5_DATA_5_IN_DATA_M 0xFFFFFFFF // Digest/Key Data 333 #define SHAMD5_DATA_5_IN_DATA_S 0 334 335 //***************************************************************************** 336 // 337 // The following are defines for the bit fields in the SHAMD5_O_DATA_6_IN 338 // register. 339 // 340 //***************************************************************************** 341 #define SHAMD5_DATA_6_IN_DATA_M 0xFFFFFFFF // Digest/Key Data 342 #define SHAMD5_DATA_6_IN_DATA_S 0 343 344 //***************************************************************************** 345 // 346 // The following are defines for the bit fields in the SHAMD5_O_DATA_7_IN 347 // register. 348 // 349 //***************************************************************************** 350 #define SHAMD5_DATA_7_IN_DATA_M 0xFFFFFFFF // Digest/Key Data 351 #define SHAMD5_DATA_7_IN_DATA_S 0 352 353 //***************************************************************************** 354 // 355 // The following are defines for the bit fields in the SHAMD5_O_DATA_8_IN 356 // register. 357 // 358 //***************************************************************************** 359 #define SHAMD5_DATA_8_IN_DATA_M 0xFFFFFFFF // Digest/Key Data 360 #define SHAMD5_DATA_8_IN_DATA_S 0 361 362 //***************************************************************************** 363 // 364 // The following are defines for the bit fields in the SHAMD5_O_DATA_9_IN 365 // register. 366 // 367 //***************************************************************************** 368 #define SHAMD5_DATA_9_IN_DATA_M 0xFFFFFFFF // Digest/Key Data 369 #define SHAMD5_DATA_9_IN_DATA_S 0 370 371 //***************************************************************************** 372 // 373 // The following are defines for the bit fields in the SHAMD5_O_DATA_10_IN 374 // register. 375 // 376 //***************************************************************************** 377 #define SHAMD5_DATA_10_IN_DATA_M \ 378 0xFFFFFFFF // Digest/Key Data 379 #define SHAMD5_DATA_10_IN_DATA_S \ 380 0 381 382 //***************************************************************************** 383 // 384 // The following are defines for the bit fields in the SHAMD5_O_DATA_11_IN 385 // register. 386 // 387 //***************************************************************************** 388 #define SHAMD5_DATA_11_IN_DATA_M \ 389 0xFFFFFFFF // Digest/Key Data 390 #define SHAMD5_DATA_11_IN_DATA_S \ 391 0 392 393 //***************************************************************************** 394 // 395 // The following are defines for the bit fields in the SHAMD5_O_DATA_12_IN 396 // register. 397 // 398 //***************************************************************************** 399 #define SHAMD5_DATA_12_IN_DATA_M \ 400 0xFFFFFFFF // Digest/Key Data 401 #define SHAMD5_DATA_12_IN_DATA_S \ 402 0 403 404 //***************************************************************************** 405 // 406 // The following are defines for the bit fields in the SHAMD5_O_DATA_13_IN 407 // register. 408 // 409 //***************************************************************************** 410 #define SHAMD5_DATA_13_IN_DATA_M \ 411 0xFFFFFFFF // Digest/Key Data 412 #define SHAMD5_DATA_13_IN_DATA_S \ 413 0 414 415 //***************************************************************************** 416 // 417 // The following are defines for the bit fields in the SHAMD5_O_DATA_14_IN 418 // register. 419 // 420 //***************************************************************************** 421 #define SHAMD5_DATA_14_IN_DATA_M \ 422 0xFFFFFFFF // Digest/Key Data 423 #define SHAMD5_DATA_14_IN_DATA_S \ 424 0 425 426 //***************************************************************************** 427 // 428 // The following are defines for the bit fields in the SHAMD5_O_DATA_15_IN 429 // register. 430 // 431 //***************************************************************************** 432 #define SHAMD5_DATA_15_IN_DATA_M \ 433 0xFFFFFFFF // Digest/Key Data 434 #define SHAMD5_DATA_15_IN_DATA_S \ 435 0 436 437 //***************************************************************************** 438 // 439 // The following are defines for the bit fields in the SHAMD5_O_REVISION 440 // register. 441 // 442 //***************************************************************************** 443 #define SHAMD5_REVISION_M 0xFFFFFFFF // Revision Number 444 #define SHAMD5_REVISION_S 0 445 446 //***************************************************************************** 447 // 448 // The following are defines for the bit fields in the SHAMD5_O_SYSCONFIG 449 // register. 450 // 451 //***************************************************************************** 452 #define SHAMD5_SYSCONFIG_SADVANCED \ 453 0x00000080 // Advanced Mode Enable 454 #define SHAMD5_SYSCONFIG_SIDLE_M \ 455 0x00000030 // Sidle mode 456 #define SHAMD5_SYSCONFIG_SIDLE_FORCE \ 457 0x00000000 // Force-idle mode 458 #define SHAMD5_SYSCONFIG_DMA_EN 0x00000008 // uDMA Request Enable 459 #define SHAMD5_SYSCONFIG_IT_EN 0x00000004 // Interrupt Enable 460 #define SHAMD5_SYSCONFIG_SOFTRESET \ 461 0x00000002 // Soft reset 462 463 //***************************************************************************** 464 // 465 // The following are defines for the bit fields in the SHAMD5_O_SYSSTATUS 466 // register. 467 // 468 //***************************************************************************** 469 #define SHAMD5_SYSSTATUS_RESETDONE \ 470 0x00000001 // Reset done status 471 472 //***************************************************************************** 473 // 474 // The following are defines for the bit fields in the SHAMD5_O_IRQSTATUS 475 // register. 476 // 477 //***************************************************************************** 478 #define SHAMD5_IRQSTATUS_CONTEXT_READY \ 479 0x00000008 // Context Ready Status 480 #define SHAMD5_IRQSTATUS_INPUT_READY \ 481 0x00000002 // Input Ready Status 482 #define SHAMD5_IRQSTATUS_OUTPUT_READY \ 483 0x00000001 // Output Ready Status 484 485 //***************************************************************************** 486 // 487 // The following are defines for the bit fields in the SHAMD5_O_IRQENABLE 488 // register. 489 // 490 //***************************************************************************** 491 #define SHAMD5_IRQENABLE_CONTEXT_READY \ 492 0x00000008 // Mask for context ready interrupt 493 #define SHAMD5_IRQENABLE_INPUT_READY \ 494 0x00000002 // Mask for input ready interrupt 495 #define SHAMD5_IRQENABLE_OUTPUT_READY \ 496 0x00000001 // Mask for output ready interrupt 497 498 //***************************************************************************** 499 // 500 // The following are defines for the bit fields in the SHAMD5_O_DMAIM register. 501 // 502 //***************************************************************************** 503 #define SHAMD5_DMAIM_COUT 0x00000004 // Context Out DMA Done Interrupt 504 // Mask 505 #define SHAMD5_DMAIM_DIN 0x00000002 // Data In DMA Done Interrupt Mask 506 #define SHAMD5_DMAIM_CIN 0x00000001 // Context In DMA Done Interrupt 507 // Mask 508 509 //***************************************************************************** 510 // 511 // The following are defines for the bit fields in the SHAMD5_O_DMARIS 512 // register. 513 // 514 //***************************************************************************** 515 #define SHAMD5_DMARIS_COUT 0x00000004 // Context Out DMA Done Raw 516 // Interrupt Status 517 #define SHAMD5_DMARIS_DIN 0x00000002 // Data In DMA Done Raw Interrupt 518 // Status 519 #define SHAMD5_DMARIS_CIN 0x00000001 // Context In DMA Done Raw 520 // Interrupt Status 521 522 //***************************************************************************** 523 // 524 // The following are defines for the bit fields in the SHAMD5_O_DMAMIS 525 // register. 526 // 527 //***************************************************************************** 528 #define SHAMD5_DMAMIS_COUT 0x00000004 // Context Out DMA Done Masked 529 // Interrupt Status 530 #define SHAMD5_DMAMIS_DIN 0x00000002 // Data In DMA Done Masked 531 // Interrupt Status 532 #define SHAMD5_DMAMIS_CIN 0x00000001 // Context In DMA Done Raw 533 // Interrupt Status 534 535 //***************************************************************************** 536 // 537 // The following are defines for the bit fields in the SHAMD5_O_DMAIC register. 538 // 539 //***************************************************************************** 540 #define SHAMD5_DMAIC_COUT 0x00000004 // Context Out DMA Done Masked 541 // Interrupt Status 542 #define SHAMD5_DMAIC_DIN 0x00000002 // Data In DMA Done Interrupt Clear 543 #define SHAMD5_DMAIC_CIN 0x00000001 // Context In DMA Done Raw 544 // Interrupt Status 545 546 #endif // __HW_SHAMD5_H__ 547