1 //***************************************************************************** 2 // 3 // hw_uart.h - Macros and defines used when accessing the UART hardware. 4 // 5 // Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Redistribution and use in source and binary forms, with or without 9 // modification, are permitted provided that the following conditions 10 // are met: 11 // 12 // Redistributions of source code must retain the above copyright 13 // notice, this list of conditions and the following disclaimer. 14 // 15 // Redistributions in binary form must reproduce the above copyright 16 // notice, this list of conditions and the following disclaimer in the 17 // documentation and/or other materials provided with the 18 // distribution. 19 // 20 // Neither the name of Texas Instruments Incorporated nor the names of 21 // its contributors may be used to endorse or promote products derived 22 // from this software without specific prior written permission. 23 // 24 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 // 36 //***************************************************************************** 37 38 #ifndef __HW_UART_H__ 39 #define __HW_UART_H__ 40 41 //***************************************************************************** 42 // 43 // The following are defines for the UART register offsets. 44 // 45 //***************************************************************************** 46 #define UART_O_DR 0x00000000 // UART Data 47 #define UART_O_RSR 0x00000004 // UART Receive Status/Error Clear 48 #define UART_O_ECR 0x00000004 // UART Receive Status/Error Clear 49 #define UART_O_FR 0x00000018 // UART Flag 50 #define UART_O_ILPR 0x00000020 // UART IrDA Low-Power Register 51 #define UART_O_IBRD 0x00000024 // UART Integer Baud-Rate Divisor 52 #define UART_O_FBRD 0x00000028 // UART Fractional Baud-Rate 53 // Divisor 54 #define UART_O_LCRH 0x0000002C // UART Line Control 55 #define UART_O_CTL 0x00000030 // UART Control 56 #define UART_O_IFLS 0x00000034 // UART Interrupt FIFO Level Select 57 #define UART_O_IM 0x00000038 // UART Interrupt Mask 58 #define UART_O_RIS 0x0000003C // UART Raw Interrupt Status 59 #define UART_O_MIS 0x00000040 // UART Masked Interrupt Status 60 #define UART_O_ICR 0x00000044 // UART Interrupt Clear 61 #define UART_O_DMACTL 0x00000048 // UART DMA Control 62 #define UART_O_9BITADDR 0x000000A4 // UART 9-Bit Self Address 63 #define UART_O_9BITAMASK 0x000000A8 // UART 9-Bit Self Address Mask 64 #define UART_O_PP 0x00000FC0 // UART Peripheral Properties 65 #define UART_O_CC 0x00000FC8 // UART Clock Configuration 66 67 //***************************************************************************** 68 // 69 // The following are defines for the bit fields in the UART_O_DR register. 70 // 71 //***************************************************************************** 72 #define UART_DR_OE 0x00000800 // UART Overrun Error 73 #define UART_DR_BE 0x00000400 // UART Break Error 74 #define UART_DR_PE 0x00000200 // UART Parity Error 75 #define UART_DR_FE 0x00000100 // UART Framing Error 76 #define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received 77 #define UART_DR_DATA_S 0 78 79 //***************************************************************************** 80 // 81 // The following are defines for the bit fields in the UART_O_RSR register. 82 // 83 //***************************************************************************** 84 #define UART_RSR_OE 0x00000008 // UART Overrun Error 85 #define UART_RSR_BE 0x00000004 // UART Break Error 86 #define UART_RSR_PE 0x00000002 // UART Parity Error 87 #define UART_RSR_FE 0x00000001 // UART Framing Error 88 89 //***************************************************************************** 90 // 91 // The following are defines for the bit fields in the UART_O_ECR register. 92 // 93 //***************************************************************************** 94 #define UART_ECR_DATA_M 0x000000FF // Error Clear 95 #define UART_ECR_DATA_S 0 96 97 //***************************************************************************** 98 // 99 // The following are defines for the bit fields in the UART_O_FR register. 100 // 101 //***************************************************************************** 102 #define UART_FR_RI 0x00000100 // Ring Indicator 103 #define UART_FR_TXFE 0x00000080 // UART Transmit FIFO Empty 104 #define UART_FR_RXFF 0x00000040 // UART Receive FIFO Full 105 #define UART_FR_TXFF 0x00000020 // UART Transmit FIFO Full 106 #define UART_FR_RXFE 0x00000010 // UART Receive FIFO Empty 107 #define UART_FR_BUSY 0x00000008 // UART Busy 108 #define UART_FR_DCD 0x00000004 // Data Carrier Detect 109 #define UART_FR_DSR 0x00000002 // Data Set Ready 110 #define UART_FR_CTS 0x00000001 // Clear To Send 111 112 //***************************************************************************** 113 // 114 // The following are defines for the bit fields in the UART_O_ILPR register. 115 // 116 //***************************************************************************** 117 #define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor 118 #define UART_ILPR_ILPDVSR_S 0 119 120 //***************************************************************************** 121 // 122 // The following are defines for the bit fields in the UART_O_IBRD register. 123 // 124 //***************************************************************************** 125 #define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor 126 #define UART_IBRD_DIVINT_S 0 127 128 //***************************************************************************** 129 // 130 // The following are defines for the bit fields in the UART_O_FBRD register. 131 // 132 //***************************************************************************** 133 #define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor 134 #define UART_FBRD_DIVFRAC_S 0 135 136 //***************************************************************************** 137 // 138 // The following are defines for the bit fields in the UART_O_LCRH register. 139 // 140 //***************************************************************************** 141 #define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select 142 #define UART_LCRH_WLEN_M 0x00000060 // UART Word Length 143 #define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default) 144 #define UART_LCRH_WLEN_6 0x00000020 // 6 bits 145 #define UART_LCRH_WLEN_7 0x00000040 // 7 bits 146 #define UART_LCRH_WLEN_8 0x00000060 // 8 bits 147 #define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs 148 #define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select 149 #define UART_LCRH_EPS 0x00000004 // UART Even Parity Select 150 #define UART_LCRH_PEN 0x00000002 // UART Parity Enable 151 #define UART_LCRH_BRK 0x00000001 // UART Send Break 152 153 //***************************************************************************** 154 // 155 // The following are defines for the bit fields in the UART_O_CTL register. 156 // 157 //***************************************************************************** 158 #define UART_CTL_CTSEN 0x00008000 // Enable Clear To Send 159 #define UART_CTL_RTSEN 0x00004000 // Enable Request to Send 160 #define UART_CTL_RTS 0x00000800 // Request to Send 161 #define UART_CTL_DTR 0x00000400 // Data Terminal Ready 162 #define UART_CTL_RXE 0x00000200 // UART Receive Enable 163 #define UART_CTL_TXE 0x00000100 // UART Transmit Enable 164 #define UART_CTL_LBE 0x00000080 // UART Loop Back Enable 165 #define UART_CTL_HSE 0x00000020 // High-Speed Enable 166 #define UART_CTL_EOT 0x00000010 // End of Transmission 167 #define UART_CTL_SMART 0x00000008 // ISO 7816 Smart Card Support 168 #define UART_CTL_SIRLP 0x00000004 // UART SIR Low-Power Mode 169 #define UART_CTL_SIREN 0x00000002 // UART SIR Enable 170 #define UART_CTL_UARTEN 0x00000001 // UART Enable 171 172 //***************************************************************************** 173 // 174 // The following are defines for the bit fields in the UART_O_IFLS register. 175 // 176 //***************************************************************************** 177 #define UART_IFLS_RX_M 0x00000038 // UART Receive Interrupt FIFO 178 // Level Select 179 #define UART_IFLS_RX1_8 0x00000000 // RX FIFO >= 1/8 full 180 #define UART_IFLS_RX2_8 0x00000008 // RX FIFO >= 1/4 full 181 #define UART_IFLS_RX4_8 0x00000010 // RX FIFO >= 1/2 full (default) 182 #define UART_IFLS_RX6_8 0x00000018 // RX FIFO >= 3/4 full 183 #define UART_IFLS_RX7_8 0x00000020 // RX FIFO >= 7/8 full 184 #define UART_IFLS_TX_M 0x00000007 // UART Transmit Interrupt FIFO 185 // Level Select 186 #define UART_IFLS_TX1_8 0x00000000 // TX FIFO <= 1/8 full 187 #define UART_IFLS_TX2_8 0x00000001 // TX FIFO <= 1/4 full 188 #define UART_IFLS_TX4_8 0x00000002 // TX FIFO <= 1/2 full (default) 189 #define UART_IFLS_TX6_8 0x00000003 // TX FIFO <= 3/4 full 190 #define UART_IFLS_TX7_8 0x00000004 // TX FIFO <= 7/8 full 191 192 //***************************************************************************** 193 // 194 // The following are defines for the bit fields in the UART_O_IM register. 195 // 196 //***************************************************************************** 197 #define UART_IM_DMATXIM 0x00020000 // Transmit DMA Interrupt Mask 198 #define UART_IM_DMARXIM 0x00010000 // Receive DMA Interrupt Mask 199 #define UART_IM_9BITIM 0x00001000 // 9-Bit Mode Interrupt Mask 200 #define UART_IM_EOTIM 0x00000800 // End of Transmission Interrupt 201 // Mask 202 #define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt 203 // Mask 204 #define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask 205 #define UART_IM_PEIM 0x00000100 // UART Parity Error Interrupt Mask 206 #define UART_IM_FEIM 0x00000080 // UART Framing Error Interrupt 207 // Mask 208 #define UART_IM_RTIM 0x00000040 // UART Receive Time-Out Interrupt 209 // Mask 210 #define UART_IM_TXIM 0x00000020 // UART Transmit Interrupt Mask 211 #define UART_IM_RXIM 0x00000010 // UART Receive Interrupt Mask 212 #define UART_IM_DSRMIM 0x00000008 // UART Data Set Ready Modem 213 // Interrupt Mask 214 #define UART_IM_DCDMIM 0x00000004 // UART Data Carrier Detect Modem 215 // Interrupt Mask 216 #define UART_IM_CTSMIM 0x00000002 // UART Clear to Send Modem 217 // Interrupt Mask 218 #define UART_IM_RIMIM 0x00000001 // UART Ring Indicator Modem 219 // Interrupt Mask 220 221 //***************************************************************************** 222 // 223 // The following are defines for the bit fields in the UART_O_RIS register. 224 // 225 //***************************************************************************** 226 #define UART_RIS_DMATXRIS 0x00020000 // Transmit DMA Raw Interrupt 227 // Status 228 #define UART_RIS_DMARXRIS 0x00010000 // Receive DMA Raw Interrupt Status 229 #define UART_RIS_9BITRIS 0x00001000 // 9-Bit Mode Raw Interrupt Status 230 #define UART_RIS_EOTRIS 0x00000800 // End of Transmission Raw 231 // Interrupt Status 232 #define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt 233 // Status 234 #define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt 235 // Status 236 #define UART_RIS_PERIS 0x00000100 // UART Parity Error Raw Interrupt 237 // Status 238 #define UART_RIS_FERIS 0x00000080 // UART Framing Error Raw Interrupt 239 // Status 240 #define UART_RIS_RTRIS 0x00000040 // UART Receive Time-Out Raw 241 // Interrupt Status 242 #define UART_RIS_TXRIS 0x00000020 // UART Transmit Raw Interrupt 243 // Status 244 #define UART_RIS_RXRIS 0x00000010 // UART Receive Raw Interrupt 245 // Status 246 #define UART_RIS_DSRRIS 0x00000008 // UART Data Set Ready Modem Raw 247 // Interrupt Status 248 #define UART_RIS_DCDRIS 0x00000004 // UART Data Carrier Detect Modem 249 // Raw Interrupt Status 250 #define UART_RIS_CTSRIS 0x00000002 // UART Clear to Send Modem Raw 251 // Interrupt Status 252 #define UART_RIS_RIRIS 0x00000001 // UART Ring Indicator Modem Raw 253 // Interrupt Status 254 255 //***************************************************************************** 256 // 257 // The following are defines for the bit fields in the UART_O_MIS register. 258 // 259 //***************************************************************************** 260 #define UART_MIS_DMATXMIS 0x00020000 // Transmit DMA Masked Interrupt 261 // Status 262 #define UART_MIS_DMARXMIS 0x00010000 // Receive DMA Masked Interrupt 263 // Status 264 #define UART_MIS_9BITMIS 0x00001000 // 9-Bit Mode Masked Interrupt 265 // Status 266 #define UART_MIS_EOTMIS 0x00000800 // End of Transmission Masked 267 // Interrupt Status 268 #define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked 269 // Interrupt Status 270 #define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked 271 // Interrupt Status 272 #define UART_MIS_PEMIS 0x00000100 // UART Parity Error Masked 273 // Interrupt Status 274 #define UART_MIS_FEMIS 0x00000080 // UART Framing Error Masked 275 // Interrupt Status 276 #define UART_MIS_RTMIS 0x00000040 // UART Receive Time-Out Masked 277 // Interrupt Status 278 #define UART_MIS_TXMIS 0x00000020 // UART Transmit Masked Interrupt 279 // Status 280 #define UART_MIS_RXMIS 0x00000010 // UART Receive Masked Interrupt 281 // Status 282 #define UART_MIS_DSRMIS 0x00000008 // UART Data Set Ready Modem Masked 283 // Interrupt Status 284 #define UART_MIS_DCDMIS 0x00000004 // UART Data Carrier Detect Modem 285 // Masked Interrupt Status 286 #define UART_MIS_CTSMIS 0x00000002 // UART Clear to Send Modem Masked 287 // Interrupt Status 288 #define UART_MIS_RIMIS 0x00000001 // UART Ring Indicator Modem Masked 289 // Interrupt Status 290 291 //***************************************************************************** 292 // 293 // The following are defines for the bit fields in the UART_O_ICR register. 294 // 295 //***************************************************************************** 296 #define UART_ICR_DMATXIC 0x00020000 // Transmit DMA Interrupt Clear 297 #define UART_ICR_DMARXIC 0x00010000 // Receive DMA Interrupt Clear 298 #define UART_ICR_9BITIC 0x00001000 // 9-Bit Mode Interrupt Clear 299 #define UART_ICR_EOTIC 0x00000800 // End of Transmission Interrupt 300 // Clear 301 #define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear 302 #define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear 303 #define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear 304 #define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear 305 #define UART_ICR_RTIC 0x00000040 // Receive Time-Out Interrupt Clear 306 #define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear 307 #define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear 308 #define UART_ICR_DSRMIC 0x00000008 // UART Data Set Ready Modem 309 // Interrupt Clear 310 #define UART_ICR_DCDMIC 0x00000004 // UART Data Carrier Detect Modem 311 // Interrupt Clear 312 #define UART_ICR_CTSMIC 0x00000002 // UART Clear to Send Modem 313 // Interrupt Clear 314 #define UART_ICR_RIMIC 0x00000001 // UART Ring Indicator Modem 315 // Interrupt Clear 316 317 //***************************************************************************** 318 // 319 // The following are defines for the bit fields in the UART_O_DMACTL register. 320 // 321 //***************************************************************************** 322 #define UART_DMACTL_DMAERR 0x00000004 // DMA on Error 323 #define UART_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable 324 #define UART_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable 325 326 //***************************************************************************** 327 // 328 // The following are defines for the bit fields in the UART_O_9BITADDR 329 // register. 330 // 331 //***************************************************************************** 332 #define UART_9BITADDR_9BITEN 0x00008000 // Enable 9-Bit Mode 333 #define UART_9BITADDR_ADDR_M 0x000000FF // Self Address for 9-Bit Mode 334 #define UART_9BITADDR_ADDR_S 0 335 336 //***************************************************************************** 337 // 338 // The following are defines for the bit fields in the UART_O_9BITAMASK 339 // register. 340 // 341 //***************************************************************************** 342 #define UART_9BITAMASK_MASK_M 0x000000FF // Self Address Mask for 9-Bit Mode 343 #define UART_9BITAMASK_MASK_S 0 344 345 //***************************************************************************** 346 // 347 // The following are defines for the bit fields in the UART_O_PP register. 348 // 349 //***************************************************************************** 350 #define UART_PP_MSE 0x00000008 // Modem Support Extended 351 #define UART_PP_MS 0x00000004 // Modem Support 352 #define UART_PP_NB 0x00000002 // 9-Bit Support 353 #define UART_PP_SC 0x00000001 // Smart Card Support 354 355 //***************************************************************************** 356 // 357 // The following are defines for the bit fields in the UART_O_CC register. 358 // 359 //***************************************************************************** 360 #define UART_CC_CS_M 0x0000000F // UART Baud Clock Source 361 #define UART_CC_CS_SYSCLK 0x00000000 // System clock (based on clock 362 // source and divisor factor) 363 #define UART_CC_CS_PIOSC 0x00000005 // PIOSC 364 365 #endif // __HW_UART_H__ 366