1 //***************************************************************************** 2 // 3 // hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware. 4 // 5 // Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Redistribution and use in source and binary forms, with or without 9 // modification, are permitted provided that the following conditions 10 // are met: 11 // 12 // Redistributions of source code must retain the above copyright 13 // notice, this list of conditions and the following disclaimer. 14 // 15 // Redistributions in binary form must reproduce the above copyright 16 // notice, this list of conditions and the following disclaimer in the 17 // documentation and/or other materials provided with the 18 // distribution. 19 // 20 // Neither the name of Texas Instruments Incorporated nor the names of 21 // its contributors may be used to endorse or promote products derived 22 // from this software without specific prior written permission. 23 // 24 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 // 36 //***************************************************************************** 37 38 #ifndef __HW_WATCHDOG_H__ 39 #define __HW_WATCHDOG_H__ 40 41 //***************************************************************************** 42 // 43 // The following are defines for the Watchdog Timer register offsets. 44 // 45 //***************************************************************************** 46 #define WDT_O_LOAD 0x00000000 // Watchdog Load 47 #define WDT_O_VALUE 0x00000004 // Watchdog Value 48 #define WDT_O_CTL 0x00000008 // Watchdog Control 49 #define WDT_O_ICR 0x0000000C // Watchdog Interrupt Clear 50 #define WDT_O_RIS 0x00000010 // Watchdog Raw Interrupt Status 51 #define WDT_O_MIS 0x00000014 // Watchdog Masked Interrupt Status 52 #define WDT_O_TEST 0x00000418 // Watchdog Test 53 #define WDT_O_LOCK 0x00000C00 // Watchdog Lock 54 55 //***************************************************************************** 56 // 57 // The following are defines for the bit fields in the WDT_O_LOAD register. 58 // 59 //***************************************************************************** 60 #define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value 61 #define WDT_LOAD_S 0 62 63 //***************************************************************************** 64 // 65 // The following are defines for the bit fields in the WDT_O_VALUE register. 66 // 67 //***************************************************************************** 68 #define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value 69 #define WDT_VALUE_S 0 70 71 //***************************************************************************** 72 // 73 // The following are defines for the bit fields in the WDT_O_CTL register. 74 // 75 //***************************************************************************** 76 #define WDT_CTL_WRC 0x80000000 // Write Complete 77 #define WDT_CTL_INTTYPE 0x00000004 // Watchdog Interrupt Type 78 #define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable 79 #define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable 80 81 //***************************************************************************** 82 // 83 // The following are defines for the bit fields in the WDT_O_ICR register. 84 // 85 //***************************************************************************** 86 #define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear 87 #define WDT_ICR_S 0 88 89 //***************************************************************************** 90 // 91 // The following are defines for the bit fields in the WDT_O_RIS register. 92 // 93 //***************************************************************************** 94 #define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status 95 96 //***************************************************************************** 97 // 98 // The following are defines for the bit fields in the WDT_O_MIS register. 99 // 100 //***************************************************************************** 101 #define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt Status 102 103 //***************************************************************************** 104 // 105 // The following are defines for the bit fields in the WDT_O_TEST register. 106 // 107 //***************************************************************************** 108 #define WDT_TEST_STALL 0x00000100 // Watchdog Stall Enable 109 110 //***************************************************************************** 111 // 112 // The following are defines for the bit fields in the WDT_O_LOCK register. 113 // 114 //***************************************************************************** 115 #define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock 116 #define WDT_LOCK_UNLOCKED 0x00000000 // Unlocked 117 #define WDT_LOCK_LOCKED 0x00000001 // Locked 118 #define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer 119 120 #endif // __HW_WATCHDOG_H__ 121