1 /*
2 * Copyright (c) 2006-2022, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2022-10-19 Nations first version
9 */
10
11 #include <rtdbg.h>
12 #include "drv_dac.h"
13
14 #ifdef RT_USING_DAC
15
16 #if defined(BSP_USING_DAC) || defined(BSP_USING_DAC1) || defined(BSP_USING_DAC2)
17
18 static struct n32_dac_config dac_config[] =
19 {
20 #if defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
21 #ifdef BSP_USING_DAC
22 {
23 "dac",
24 },
25 #endif
26 #endif
27
28 #ifdef BSP_USING_DAC1
29 {
30 "dac1",
31 DAC_CHANNEL_1,
32 },
33 #endif
34
35 #ifdef BSP_USING_DAC2
36 {
37 "dac2",
38 DAC_CHANNEL_2,
39 },
40 #endif
41 };
42
43
44 static struct n32_dac dac_obj[sizeof(dac_config) / sizeof(dac_config[0])];
45
n32_dac_init(struct n32_dac_config * config)46 static void n32_dac_init(struct n32_dac_config *config)
47 {
48 DAC_InitType DAC_InitStructure;
49
50 /* DAC Periph clock enable */
51 RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_DAC, ENABLE);
52
53 /* DAC channel Configuration */
54 DAC_InitStructure.Trigger = DAC_TRG_SOFTWARE;
55 DAC_InitStructure.WaveGen = DAC_WAVEGEN_NOISE;
56 DAC_InitStructure.LfsrUnMaskTriAmp = DAC_UNMASK_LFSRBIT0;
57 DAC_InitStructure.BufferOutput = DAC_BUFFOUTPUT_ENABLE;
58
59 #if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR)
60 DAC_Init(config->dac_periph, &DAC_InitStructure);
61 #elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
62 DAC_Init(&DAC_InitStructure);
63
64 /* Enable DAC */
65 DAC_Enable(ENABLE);
66
67 /* Set DAC Channel DR12CH register */
68 DAC_SetChData(DAC_ALIGN_R_12BIT, 4094);
69 #endif
70 }
71
n32_dac_enabled(struct rt_dac_device * device,rt_uint32_t channel)72 static rt_err_t n32_dac_enabled(struct rt_dac_device *device, rt_uint32_t channel)
73 {
74 RT_ASSERT(device != RT_NULL);
75
76 #if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR)
77 DAC_Enable(channel, ENABLE);
78 #elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
79 DAC_Enable(ENABLE);
80 #endif
81
82 return RT_EOK;
83 }
84
n32_dac_disabled(struct rt_dac_device * device,rt_uint32_t channel)85 static rt_err_t n32_dac_disabled(struct rt_dac_device *device, rt_uint32_t channel)
86 {
87 RT_ASSERT(device != RT_NULL);
88
89 #if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR)
90 DAC_Enable(channel, DISABLE);
91 #elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
92 DAC_Enable(DISABLE);
93 #endif
94
95 return RT_EOK;
96 }
97
98
n32_set_dac_value(struct rt_dac_device * device,rt_uint32_t channel,rt_uint32_t * value)99 static rt_err_t n32_set_dac_value(struct rt_dac_device *device, rt_uint32_t channel, rt_uint32_t *value)
100 {
101 RT_ASSERT(device != RT_NULL);
102 rt_uint16_t set_value = 0;
103 set_value = (rt_uint16_t)*value;
104
105 #if defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
106 /* Start DAC Channel conversion by software */
107 DAC_SoftTrgEnable(ENABLE);
108 #endif
109 if (set_value > 4096)
110 {
111 set_value = 4096;
112 }
113
114 #if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR)
115 /* Start DAC Channel conversion by software */
116 if (channel == DAC_CHANNEL_1)
117 {
118 DAC_SetCh1Data(DAC_ALIGN_R_12BIT, set_value);
119 DAC_SoftTrgEnable(DAC_CHANNEL_1, ENABLE);
120 }
121 else
122 {
123 DAC_SetCh2Data(DAC_ALIGN_R_12BIT, set_value);
124 DAC_SoftTrgEnable(DAC_CHANNEL_2, ENABLE);
125 }
126 #elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
127 DAC_SetChData(DAC_ALIGN_R_12BIT, set_value);
128 #endif
129 return RT_EOK;
130 }
131
132 static const struct rt_dac_ops n32_dac_ops =
133 {
134 .disabled = n32_dac_disabled,
135 .enabled = n32_dac_enabled,
136 .convert = n32_set_dac_value,
137 };
138
139
rt_hw_dac_init(void)140 int rt_hw_dac_init(void)
141 {
142 GPIO_InitType GPIO_InitStructure;
143
144 int result = RT_EOK;
145 /* save dac name */
146 char name_buf[5] = {'d', 'a', 'c', '0', 0};
147 int i = 0;
148
149 for (i = 0; i < sizeof(dac_config) / sizeof(dac_config[0]); i++)
150 {
151 /* dac init */
152 dac_obj[i].config = &dac_config[i];
153
154 #if defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
155 #if defined(BSP_USING_DAC)
156 name_buf[3] = '\0';
157
158 /* Enable GPIO clock */
159 RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
160
161 GPIO_InitStruct(&GPIO_InitStructure);
162
163 /* Config DAC chennel */
164 GPIO_InitStructure.Pin = GPIO_PIN_4;
165 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Input;
166 GPIO_InitPeripheral(GPIOA, &GPIO_InitStructure);
167 #endif
168 #endif
169
170 #ifdef BSP_USING_DAC1
171 if (dac_obj[i].config->dac_periph == DAC_CHANNEL_1)
172 {
173 name_buf[3] = '1';
174
175 RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
176
177 GPIO_InitStruct(&GPIO_InitStructure);
178 /* Configure PA4 DAC1 */
179 GPIO_InitStructure.Pin = GPIO_PIN_4;
180 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
181 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
182 GPIO_InitPeripheral(GPIOA, &GPIO_InitStructure);
183 }
184
185 #endif
186
187 #ifdef BSP_USING_DAC2
188 if (dac_obj[i].config->dac_periph == DAC_CHANNEL_2)
189 {
190 name_buf[3] = '2';
191
192 RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
193
194 GPIO_InitStruct(&GPIO_InitStructure);
195 /* Configure PA5 DAC1 */
196 GPIO_InitStructure.Pin = GPIO_PIN_5;
197 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
198 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
199 GPIO_InitPeripheral(GPIOA, &GPIO_InitStructure);
200 }
201 #endif
202
203 /* register dac device */
204 n32_dac_init(&dac_config[i]);
205 if (rt_hw_dac_register(&dac_obj[i].dac_device, name_buf, &n32_dac_ops, &dac_obj[i].config->dac_periph) == RT_EOK)
206 {
207 LOG_D("%s init success", name_buf);
208 }
209 else
210 {
211 LOG_E("%s register failed", name_buf);
212 result = -RT_ERROR;
213 }
214 }
215
216 return result;
217 }
218 INIT_DEVICE_EXPORT(rt_hw_dac_init);
219
220 #endif /* defined(BSP_USING_DAC1) || defined(BSP_USING_DAC2) */
221 #endif /* RT_USING_DAC */
222