1 /*
2 * Copyright (c) 2006-2022, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2022-10-19 Nations first version
9 */
10
11 #include <rtdevice.h>
12 #include <rthw.h>
13 #include "board.h"
14 #include "drv_gpio.h"
15
16 #ifdef RT_USING_PIN
17
18 static const struct pin_index pins[] =
19 {
20 #if defined(GPIOA)
21 __N32_PIN(0 , GPIOA, GPIO_PIN_0 ),
22 __N32_PIN(1 , GPIOA, GPIO_PIN_1 ),
23 __N32_PIN(2 , GPIOA, GPIO_PIN_2 ),
24 __N32_PIN(3 , GPIOA, GPIO_PIN_3 ),
25 __N32_PIN(4 , GPIOA, GPIO_PIN_4 ),
26 __N32_PIN(5 , GPIOA, GPIO_PIN_5 ),
27 __N32_PIN(6 , GPIOA, GPIO_PIN_6 ),
28 __N32_PIN(7 , GPIOA, GPIO_PIN_7 ),
29 __N32_PIN(8 , GPIOA, GPIO_PIN_8 ),
30 __N32_PIN(9 , GPIOA, GPIO_PIN_9 ),
31 __N32_PIN(10, GPIOA, GPIO_PIN_10),
32 __N32_PIN(11, GPIOA, GPIO_PIN_11),
33 __N32_PIN(12, GPIOA, GPIO_PIN_12),
34 __N32_PIN(13, GPIOA, GPIO_PIN_13),
35 __N32_PIN(14, GPIOA, GPIO_PIN_14),
36 __N32_PIN(15, GPIOA, GPIO_PIN_15),
37 #if defined(GPIOB)
38 __N32_PIN(16, GPIOB, GPIO_PIN_0),
39 __N32_PIN(17, GPIOB, GPIO_PIN_1),
40 __N32_PIN(18, GPIOB, GPIO_PIN_2),
41 __N32_PIN(19, GPIOB, GPIO_PIN_3),
42 __N32_PIN(20, GPIOB, GPIO_PIN_4),
43 __N32_PIN(21, GPIOB, GPIO_PIN_5),
44 __N32_PIN(22, GPIOB, GPIO_PIN_6),
45 __N32_PIN(23, GPIOB, GPIO_PIN_7),
46 __N32_PIN(24, GPIOB, GPIO_PIN_8),
47 __N32_PIN(25, GPIOB, GPIO_PIN_9),
48 __N32_PIN(26, GPIOB, GPIO_PIN_10),
49 __N32_PIN(27, GPIOB, GPIO_PIN_11),
50 __N32_PIN(28, GPIOB, GPIO_PIN_12),
51 __N32_PIN(29, GPIOB, GPIO_PIN_13),
52 __N32_PIN(30, GPIOB, GPIO_PIN_14),
53 __N32_PIN(31, GPIOB, GPIO_PIN_15),
54 #if defined(GPIOC)
55 __N32_PIN(32, GPIOC, GPIO_PIN_0),
56 __N32_PIN(33, GPIOC, GPIO_PIN_1),
57 __N32_PIN(34, GPIOC, GPIO_PIN_2),
58 __N32_PIN(35, GPIOC, GPIO_PIN_3),
59 __N32_PIN(36, GPIOC, GPIO_PIN_4),
60 __N32_PIN(37, GPIOC, GPIO_PIN_5),
61 __N32_PIN(38, GPIOC, GPIO_PIN_6),
62 __N32_PIN(39, GPIOC, GPIO_PIN_7),
63 __N32_PIN(40, GPIOC, GPIO_PIN_8),
64 __N32_PIN(41, GPIOC, GPIO_PIN_9),
65 __N32_PIN(42, GPIOC, GPIO_PIN_10),
66 __N32_PIN(43, GPIOC, GPIO_PIN_11),
67 __N32_PIN(44, GPIOC, GPIO_PIN_12),
68 __N32_PIN(45, GPIOC, GPIO_PIN_13),
69 __N32_PIN(46, GPIOC, GPIO_PIN_14),
70 __N32_PIN(47, GPIOC, GPIO_PIN_15),
71 #if defined(GPIOD)
72 __N32_PIN(48, GPIOD, GPIO_PIN_0),
73 __N32_PIN(49, GPIOD, GPIO_PIN_1),
74 __N32_PIN(50, GPIOD, GPIO_PIN_2),
75 __N32_PIN(51, GPIOD, GPIO_PIN_3),
76 __N32_PIN(52, GPIOD, GPIO_PIN_4),
77 __N32_PIN(53, GPIOD, GPIO_PIN_5),
78 __N32_PIN(54, GPIOD, GPIO_PIN_6),
79 __N32_PIN(55, GPIOD, GPIO_PIN_7),
80 __N32_PIN(56, GPIOD, GPIO_PIN_8),
81 __N32_PIN(57, GPIOD, GPIO_PIN_9),
82 __N32_PIN(58, GPIOD, GPIO_PIN_10),
83 __N32_PIN(59, GPIOD, GPIO_PIN_11),
84 __N32_PIN(60, GPIOD, GPIO_PIN_12),
85 __N32_PIN(61, GPIOD, GPIO_PIN_13),
86 __N32_PIN(62, GPIOD, GPIO_PIN_14),
87 __N32_PIN(63, GPIOD, GPIO_PIN_15),
88 #if defined(GPIOE)
89 __N32_PIN(64, GPIOE, GPIO_PIN_0),
90 __N32_PIN(65, GPIOE, GPIO_PIN_1),
91 __N32_PIN(66, GPIOE, GPIO_PIN_2),
92 __N32_PIN(67, GPIOE, GPIO_PIN_3),
93 __N32_PIN(68, GPIOE, GPIO_PIN_4),
94 __N32_PIN(69, GPIOE, GPIO_PIN_5),
95 __N32_PIN(70, GPIOE, GPIO_PIN_6),
96 __N32_PIN(71, GPIOE, GPIO_PIN_7),
97 __N32_PIN(72, GPIOE, GPIO_PIN_8),
98 __N32_PIN(73, GPIOE, GPIO_PIN_9),
99 __N32_PIN(74, GPIOE, GPIO_PIN_10),
100 __N32_PIN(75, GPIOE, GPIO_PIN_11),
101 __N32_PIN(76, GPIOE, GPIO_PIN_12),
102 __N32_PIN(77, GPIOE, GPIO_PIN_13),
103 __N32_PIN(78, GPIOE, GPIO_PIN_14),
104 __N32_PIN(79, GPIOE, GPIO_PIN_15),
105 #if defined(GPIOF)
106 __N32_PIN(80, GPIOF, GPIO_PIN_0),
107 __N32_PIN(81, GPIOF, GPIO_PIN_1),
108 __N32_PIN(82, GPIOF, GPIO_PIN_2),
109 __N32_PIN(83, GPIOF, GPIO_PIN_3),
110 __N32_PIN(84, GPIOF, GPIO_PIN_4),
111 __N32_PIN(85, GPIOF, GPIO_PIN_5),
112 __N32_PIN(86, GPIOF, GPIO_PIN_6),
113 __N32_PIN(87, GPIOF, GPIO_PIN_7),
114 __N32_PIN(88, GPIOF, GPIO_PIN_8),
115 __N32_PIN(89, GPIOF, GPIO_PIN_9),
116 __N32_PIN(90, GPIOF, GPIO_PIN_10),
117 __N32_PIN(91, GPIOF, GPIO_PIN_11),
118 __N32_PIN(92, GPIOF, GPIO_PIN_12),
119 __N32_PIN(93, GPIOF, GPIO_PIN_13),
120 __N32_PIN(94, GPIOF, GPIO_PIN_14),
121 __N32_PIN(95, GPIOF, GPIO_PIN_15),
122 #if defined(GPIOG)
123 __N32_PIN(96, GPIOG, GPIO_PIN_0),
124 __N32_PIN(97, GPIOG, GPIO_PIN_1),
125 __N32_PIN(98, GPIOG, GPIO_PIN_2),
126 __N32_PIN(99, GPIOG, GPIO_PIN_3),
127 __N32_PIN(100, GPIOG, GPIO_PIN_4),
128 __N32_PIN(101, GPIOG, GPIO_PIN_5),
129 __N32_PIN(102, GPIOG, GPIO_PIN_6),
130 __N32_PIN(103, GPIOG, GPIO_PIN_7),
131 __N32_PIN(104, GPIOG, GPIO_PIN_8),
132 __N32_PIN(105, GPIOG, GPIO_PIN_9),
133 __N32_PIN(106, GPIOG, GPIO_PIN_10),
134 __N32_PIN(107, GPIOG, GPIO_PIN_11),
135 __N32_PIN(108, GPIOG, GPIO_PIN_12),
136 __N32_PIN(109, GPIOG, GPIO_PIN_13),
137 __N32_PIN(110, GPIOG, GPIO_PIN_14),
138 __N32_PIN(111, GPIOG, GPIO_PIN_15),
139
140 #endif /* defined(GPIOG) */
141 #endif /* defined(GPIOF) */
142 #endif /* defined(GPIOE) */
143 #endif /* defined(GPIOD) */
144 #endif /* defined(GPIOC) */
145 #endif /* defined(GPIOB) */
146 #endif /* defined(GPIOA) */
147 };
148
149 static const struct pin_irq_map pin_irq_map[] =
150 {
151 {GPIO_PIN_0, EXTI0_IRQn},
152 {GPIO_PIN_1, EXTI1_IRQn},
153 {GPIO_PIN_2, EXTI2_IRQn},
154 {GPIO_PIN_3, EXTI3_IRQn},
155 {GPIO_PIN_4, EXTI4_IRQn},
156 {GPIO_PIN_5, EXTI9_5_IRQn},
157 {GPIO_PIN_6, EXTI9_5_IRQn},
158 {GPIO_PIN_7, EXTI9_5_IRQn},
159 {GPIO_PIN_8, EXTI9_5_IRQn},
160 {GPIO_PIN_9, EXTI9_5_IRQn},
161 {GPIO_PIN_10, EXTI15_10_IRQn},
162 {GPIO_PIN_11, EXTI15_10_IRQn},
163 {GPIO_PIN_12, EXTI15_10_IRQn},
164 {GPIO_PIN_13, EXTI15_10_IRQn},
165 {GPIO_PIN_14, EXTI15_10_IRQn},
166 {GPIO_PIN_15, EXTI15_10_IRQn},
167 };
168
169 static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
170 {
171 {-1, 0, RT_NULL, RT_NULL},
172 {-1, 0, RT_NULL, RT_NULL},
173 {-1, 0, RT_NULL, RT_NULL},
174 {-1, 0, RT_NULL, RT_NULL},
175 {-1, 0, RT_NULL, RT_NULL},
176 {-1, 0, RT_NULL, RT_NULL},
177 {-1, 0, RT_NULL, RT_NULL},
178 {-1, 0, RT_NULL, RT_NULL},
179 {-1, 0, RT_NULL, RT_NULL},
180 {-1, 0, RT_NULL, RT_NULL},
181 {-1, 0, RT_NULL, RT_NULL},
182 {-1, 0, RT_NULL, RT_NULL},
183 {-1, 0, RT_NULL, RT_NULL},
184 {-1, 0, RT_NULL, RT_NULL},
185 {-1, 0, RT_NULL, RT_NULL},
186 {-1, 0, RT_NULL, RT_NULL},
187 };
188 static uint32_t pin_irq_enable_mask=0;
189
190 #define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
get_pin(uint8_t pin)191 static const struct pin_index *get_pin(uint8_t pin)
192 {
193 const struct pin_index *index;
194
195 if (pin < ITEM_NUM(pins))
196 {
197 index = &pins[pin];
198 if (index->index == -1)
199 index = RT_NULL;
200 }
201 else
202 {
203 index = RT_NULL;
204 }
205
206 return index;
207 };
208
n32_pin_write(rt_device_t dev,rt_base_t pin,rt_uint8_t value)209 static void n32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
210 {
211 const struct pin_index *index;
212
213 index = get_pin(pin);
214 if (index == RT_NULL)
215 {
216 return;
217 }
218 GPIO_WriteBit(index->gpio, index->pin, (Bit_OperateType)value);
219 }
220
n32_pin_read(rt_device_t dev,rt_base_t pin)221 static rt_ssize_t n32_pin_read(rt_device_t dev, rt_base_t pin)
222 {
223 rt_ssize_t value;
224 const struct pin_index *index;
225
226 value = PIN_LOW;
227
228 index = get_pin(pin);
229 if (index == RT_NULL)
230 {
231 return -RT_EINVAL;
232 }
233
234 value = GPIO_ReadInputDataBit(index->gpio, index->pin);
235
236 return value;
237 }
238
n32_gpio_clock_enable(GPIO_Module * GPIOx)239 static void n32_gpio_clock_enable(GPIO_Module* GPIOx)
240 {
241 /* Enable the GPIO Clock */
242 if (GPIOx == GPIOA)
243 {
244 RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
245 }
246 else if (GPIOx == GPIOB)
247 {
248 RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE);
249 }
250 else if (GPIOx == GPIOC)
251 {
252 RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOC, ENABLE);
253 }
254 else if (GPIOx == GPIOD)
255 {
256 RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOD, ENABLE);
257 }
258 #if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR)
259 else if (GPIOx == GPIOE)
260 {
261 RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOE, ENABLE);
262 }
263 #endif
264 #ifdef SOC_N32G45X
265 else if (GPIOx == GPIOF)
266 {
267 RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOF, ENABLE);
268 }
269 else if (GPIOx == GPIOG)
270 {
271 RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOG, ENABLE);
272 }
273 #endif /* SOC_N32G45X */
274 else
275 {
276 rt_kprintf("The GPIO port number is incorrect. No GPIO port exists\n");
277 }
278 }
279
n32_pin_mode(rt_device_t dev,rt_base_t pin,rt_uint8_t mode)280 static void n32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
281 {
282 const struct pin_index *index;
283 GPIO_InitType GPIO_InitStructure;
284
285 index = get_pin(pin);
286 if (index == RT_NULL)
287 {
288 return;
289 }
290
291 /* Enable the GPIO Clock */
292 n32_gpio_clock_enable(index->gpio);
293
294 GPIO_InitStruct(&GPIO_InitStructure);
295
296 /* Configure GPIO_InitStructure */
297 GPIO_InitStructure.Pin = index->pin;
298
299 #if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR)
300 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
301 #endif
302
303 if (mode == PIN_MODE_OUTPUT)
304 {
305 /* output setting */
306 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
307 }
308 else if (mode == PIN_MODE_INPUT)
309 {
310 /* input setting: not pull. */
311 #if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR)
312 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
313 #elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
314 GPIO_InitStructure.GPIO_Pull = GPIO_No_Pull;
315 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Input;
316 #endif
317 }
318 else if (mode == PIN_MODE_INPUT_PULLUP)
319 {
320 /* input setting: pull up. */
321 #if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR)
322 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
323 #elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
324 GPIO_InitStructure.GPIO_Pull = GPIO_Pull_Up;
325 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Input;
326 #endif
327 }
328 else if (mode == PIN_MODE_INPUT_PULLDOWN)
329 {
330 /* input setting: pull down. */
331 #if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR)
332 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
333 #elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
334 GPIO_InitStructure.GPIO_Pull = GPIO_Pull_Down;
335 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Input;
336 #endif
337 }
338 else if (mode == PIN_MODE_OUTPUT_OD)
339 {
340 /* output setting: od. */
341 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_OD;
342 }
343 #if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR)
344 GPIO_InitPeripheral(index->gpio, &GPIO_InitStructure);
345 #elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
346 GPIO_InitPeripheral(index->gpio, &GPIO_InitStructure);
347 #endif
348
349 }
350
bit2bitno(rt_uint32_t bit)351 rt_inline rt_int32_t bit2bitno(rt_uint32_t bit)
352 {
353 int i;
354 for (i = 0; i < 32; i++)
355 {
356 if ((0x01 << i) == bit)
357 {
358 return i;
359 }
360 }
361 return -1;
362 }
363
port2portsource(GPIO_Module * module)364 rt_inline rt_int32_t port2portsource(GPIO_Module* module)
365 {
366 if (module == GPIOA)
367 {
368 return GPIOA_PORT_SOURCE;
369 }
370 else if (module == GPIOB)
371 {
372 return GPIOB_PORT_SOURCE;
373 }
374 else if (module == GPIOC)
375 {
376 return GPIOC_PORT_SOURCE;
377 }
378 else if (module == GPIOD)
379 {
380 return GPIOD_PORT_SOURCE;
381 }
382 #if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR)
383 else if (module == GPIOE)
384 {
385 return GPIOE_PORT_SOURCE;
386 }
387 #endif
388 #ifdef SOC_N32G45X
389 else if (module == GPIOF)
390 {
391 return GPIOF_PORT_SOURCE;
392 }
393 else if (module == GPIOG)
394 {
395 return GPIOG_PORT_SOURCE;
396 }
397 #endif /* SOC_N32G45X */
398 else
399 {
400 rt_kprintf("The GPIO port number is incorrect. No GPIO port exists\n");
401 return -RT_ERROR;
402 }
403 }
404
get_pin_irq_map(uint32_t pinbit)405 rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
406 {
407 rt_int32_t mapindex = bit2bitno(pinbit);
408 if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map))
409 {
410 return RT_NULL;
411 }
412 return &pin_irq_map[mapindex];
413 };
414
n32_pin_attach_irq(struct rt_device * device,rt_base_t pin,rt_uint8_t mode,void (* hdr)(void * args),void * args)415 static rt_err_t n32_pin_attach_irq(struct rt_device *device, rt_base_t pin,
416 rt_uint8_t mode, void (*hdr)(void *args), void *args)
417 {
418 const struct pin_index *index;
419 rt_base_t level;
420 rt_int32_t irqindex = -1;
421
422 index = get_pin(pin);
423 if (index == RT_NULL)
424 {
425 return -RT_ENOSYS;
426 }
427 irqindex = bit2bitno(index->pin);
428 if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
429 {
430 return -RT_ENOSYS;
431 }
432
433 level = rt_hw_interrupt_disable();
434 if (pin_irq_hdr_tab[irqindex].pin == pin &&
435 pin_irq_hdr_tab[irqindex].hdr == hdr &&
436 pin_irq_hdr_tab[irqindex].mode == mode &&
437 pin_irq_hdr_tab[irqindex].args == args)
438 {
439 rt_hw_interrupt_enable(level);
440 return RT_EOK;
441 }
442 if (pin_irq_hdr_tab[irqindex].pin != -1)
443 {
444 rt_hw_interrupt_enable(level);
445 return -RT_EBUSY;
446 }
447 pin_irq_hdr_tab[irqindex].pin = pin;
448 pin_irq_hdr_tab[irqindex].hdr = hdr;
449 pin_irq_hdr_tab[irqindex].mode = mode;
450 pin_irq_hdr_tab[irqindex].args = args;
451 rt_hw_interrupt_enable(level);
452
453 return RT_EOK;
454 }
455
n32_pin_dettach_irq(struct rt_device * device,rt_base_t pin)456 static rt_err_t n32_pin_dettach_irq(struct rt_device *device, rt_base_t pin)
457 {
458 const struct pin_index *index;
459 rt_base_t level;
460 rt_int32_t irqindex = -1;
461
462 index = get_pin(pin);
463 if (index == RT_NULL)
464 {
465 return -RT_ENOSYS;
466 }
467 irqindex = bit2bitno(index->pin);
468 if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
469 {
470 return -RT_ENOSYS;
471 }
472
473 level = rt_hw_interrupt_disable();
474 if (pin_irq_hdr_tab[irqindex].pin == -1)
475 {
476 rt_hw_interrupt_enable(level);
477 return RT_EOK;
478 }
479 pin_irq_hdr_tab[irqindex].pin = -1;
480 pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
481 pin_irq_hdr_tab[irqindex].mode = 0;
482 pin_irq_hdr_tab[irqindex].args = RT_NULL;
483 rt_hw_interrupt_enable(level);
484
485 return RT_EOK;
486 }
487
n32_pin_irq_enable(struct rt_device * device,rt_base_t pin,rt_uint8_t enabled)488 static rt_err_t n32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
489 rt_uint8_t enabled)
490 {
491 const struct pin_index *index;
492 const struct pin_irq_map *irqmap;
493 rt_base_t level;
494 rt_int32_t irqindex = -1;
495 EXTI_InitType EXTI_InitStructure;
496
497 index = get_pin(pin);
498 if (index == RT_NULL)
499 {
500 return -RT_ENOSYS;
501 }
502
503 if (enabled == PIN_IRQ_ENABLE)
504 {
505 irqindex = bit2bitno(index->pin);
506 if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
507 {
508 return -RT_ENOSYS;
509 }
510
511 level = rt_hw_interrupt_disable();
512
513 if (pin_irq_hdr_tab[irqindex].pin == -1)
514 {
515 rt_hw_interrupt_enable(level);
516 return -RT_ENOSYS;
517 }
518
519 irqmap = &pin_irq_map[irqindex];
520
521 switch (pin_irq_hdr_tab[irqindex].mode)
522 {
523 case PIN_IRQ_MODE_RISING:
524 EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
525 break;
526
527 case PIN_IRQ_MODE_FALLING:
528 EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
529 break;
530
531 case PIN_IRQ_MODE_RISING_FALLING:
532 EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling;
533 break;
534
535 default:
536 return -RT_ERROR;
537 }
538
539 RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
540 /* configure EXTI line */
541 GPIO_ConfigEXTILine(port2portsource(index->gpio), irqindex);
542
543 /*Configure key EXTI line*/
544 EXTI_InitStructure.EXTI_Line = index->pin;
545 EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
546 EXTI_InitStructure.EXTI_LineCmd = ENABLE;
547 EXTI_InitPeripheral(&EXTI_InitStructure);
548
549 EXTI_ClrITPendBit(index->pin);
550
551 /* enable and set interrupt priority */
552 NVIC_SetPriority(irqmap->irqno, 5);
553 NVIC_EnableIRQ(irqmap->irqno);
554
555 pin_irq_enable_mask |= irqmap->pinbit;
556
557 rt_hw_interrupt_enable(level);
558 }
559 else if (enabled == PIN_IRQ_DISABLE)
560 {
561 irqmap = get_pin_irq_map(index->pin);
562 if (irqmap == RT_NULL)
563 {
564 return -RT_ENOSYS;
565 }
566
567 level = rt_hw_interrupt_disable();
568
569 pin_irq_enable_mask &= ~irqmap->pinbit;
570 if (( irqmap->pinbit>=GPIO_PIN_5 )&&( irqmap->pinbit<=GPIO_PIN_9 ))
571 {
572 if (!(pin_irq_enable_mask&(GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9)))
573 {
574 NVIC_DisableIRQ(irqmap->irqno);
575 }
576 }
577 else if (( irqmap->pinbit>=GPIO_PIN_10 )&&( irqmap->pinbit<=GPIO_PIN_15 ))
578 {
579 if (!(pin_irq_enable_mask&(GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15)))
580 {
581 NVIC_DisableIRQ(irqmap->irqno);
582 }
583 }
584 else
585 {
586 NVIC_DisableIRQ(irqmap->irqno);
587 }
588
589 rt_hw_interrupt_enable(level);
590 }
591 else
592 {
593 return -RT_ENOSYS;
594 }
595
596 return RT_EOK;
597 }
598 const static struct rt_pin_ops _n32_pin_ops =
599 {
600 n32_pin_mode,
601 n32_pin_write,
602 n32_pin_read,
603 n32_pin_attach_irq,
604 n32_pin_dettach_irq,
605 n32_pin_irq_enable,
606 };
607
rt_hw_pin_init(void)608 int rt_hw_pin_init(void)
609 {
610 return rt_device_pin_register("pin", &_n32_pin_ops, RT_NULL);
611 }
612 INIT_BOARD_EXPORT(rt_hw_pin_init);
613
pin_irq_hdr(int irqno)614 rt_inline void pin_irq_hdr(int irqno)
615 {
616 if (pin_irq_hdr_tab[irqno].hdr)
617 {
618 pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
619 }
620 }
621
N32_GPIO_EXTI_IRQHandler(rt_int8_t exti_line)622 void N32_GPIO_EXTI_IRQHandler(rt_int8_t exti_line)
623 {
624 if (RESET != EXTI_GetITStatus(1 << exti_line))
625 {
626 pin_irq_hdr(exti_line);
627 EXTI_ClrITPendBit(1 << exti_line);
628 }
629 }
630
EXTI0_IRQHandler(void)631 void EXTI0_IRQHandler(void)
632 {
633 rt_interrupt_enter();
634 N32_GPIO_EXTI_IRQHandler(0);
635 rt_interrupt_leave();
636 }
EXTI1_IRQHandler(void)637 void EXTI1_IRQHandler(void)
638 {
639 rt_interrupt_enter();
640 N32_GPIO_EXTI_IRQHandler(1);
641 rt_interrupt_leave();
642 }
EXTI2_IRQHandler(void)643 void EXTI2_IRQHandler(void)
644 {
645 rt_interrupt_enter();
646 N32_GPIO_EXTI_IRQHandler(2);
647 rt_interrupt_leave();
648 }
EXTI3_IRQHandler(void)649 void EXTI3_IRQHandler(void)
650 {
651 rt_interrupt_enter();
652 N32_GPIO_EXTI_IRQHandler(3);
653 rt_interrupt_leave();
654 }
EXTI4_IRQHandler(void)655 void EXTI4_IRQHandler(void)
656 {
657 rt_interrupt_enter();
658 N32_GPIO_EXTI_IRQHandler(4);
659 rt_interrupt_leave();
660 }
EXTI9_5_IRQHandler(void)661 void EXTI9_5_IRQHandler(void)
662 {
663 rt_interrupt_enter();
664 N32_GPIO_EXTI_IRQHandler(5);
665 N32_GPIO_EXTI_IRQHandler(6);
666 N32_GPIO_EXTI_IRQHandler(7);
667 N32_GPIO_EXTI_IRQHandler(8);
668 N32_GPIO_EXTI_IRQHandler(9);
669 rt_interrupt_leave();
670 }
EXTI15_10_IRQHandler(void)671 void EXTI15_10_IRQHandler(void)
672 {
673 rt_interrupt_enter();
674 N32_GPIO_EXTI_IRQHandler(10);
675 N32_GPIO_EXTI_IRQHandler(11);
676 N32_GPIO_EXTI_IRQHandler(12);
677 N32_GPIO_EXTI_IRQHandler(13);
678 N32_GPIO_EXTI_IRQHandler(14);
679 N32_GPIO_EXTI_IRQHandler(15);
680 rt_interrupt_leave();
681 }
682
683 #endif /* RT_USING_PIN */
684