1 /*
2 * Copyright (c) 2006-2020, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2020-06-08 hqfang the first version.
9 *
10 */
11 #include "drv_wdt.h"
12
13 #ifdef BSP_USING_WDT
14
15
gd32_wdog_close(rt_watchdog_t * wdt)16 static rt_err_t gd32_wdog_close(rt_watchdog_t *wdt)
17 {
18 rt_uint32_t level;
19
20 level = rt_hw_interrupt_disable();
21 rcu_osci_off(RCU_IRC40K);
22 rt_hw_interrupt_enable(level);
23
24 return RT_EOK;
25 }
26
gd32_wdog_open(rt_watchdog_t * wdt,rt_uint16_t oflag)27 static rt_err_t gd32_wdog_open(rt_watchdog_t *wdt, rt_uint16_t oflag)
28 {
29 rt_uint32_t level;
30
31 level = rt_hw_interrupt_disable();
32 /* enable IRC40K */
33 rcu_osci_on(RCU_IRC40K);
34 /* wait till IRC40K is ready */
35 while (SUCCESS != rcu_osci_stab_wait(RCU_IRC40K));
36 fwdgt_counter_reload();
37 fwdgt_enable();
38 rt_hw_interrupt_enable(level);
39
40 return RT_EOK;
41 }
42
gd32_wdog_init(rt_watchdog_t * wdt)43 static rt_err_t gd32_wdog_init(rt_watchdog_t *wdt)
44 {
45 /* confiure FWDGT counter clock: 40KHz(IRC40K) / 256 = 0.15625 KHz */
46 fwdgt_config(FWDGT_RLD_RLD, FWDGT_PSC_DIV256);
47 fwdgt_enable();
48 return RT_EOK;
49 }
50
gd32_wdog_refresh(rt_watchdog_t * wdt)51 static rt_err_t gd32_wdog_refresh(rt_watchdog_t *wdt)
52 {
53 rt_uint32_t level;
54
55 level = rt_hw_interrupt_disable();
56 fwdgt_counter_reload();
57 rt_hw_interrupt_enable(level);
58
59 return RT_EOK;
60 }
61
62 /**
63 * @function control wdog
64 *
65 * @param
66 * wdt whick wdog used
67 * cmd control wdog options
68 * args argument of conrtol
69 * @retval rt_err_t the status of control result
70 *
71 *
72 */
73 #define WDT_RELOAD_SECOND ((FWDGT_RLD & FWDGT_RLD_RLD) / 156)
gd32_wdog_control(rt_watchdog_t * wdt,int cmd,void * args)74 static rt_err_t gd32_wdog_control(rt_watchdog_t *wdt, int cmd, void *args)
75 {
76 RT_ASSERT(wdt != NULL);
77
78 uint16_t reload_value;
79 static uint16_t wdt_started = 0;
80 static rt_tick_t last_tick = 0;
81
82 switch (cmd)
83 {
84 case RT_DEVICE_CTRL_WDT_GET_TIMEOUT:
85 {
86 *(uint16_t *)args = WDT_RELOAD_SECOND;
87 }
88 break;
89 case RT_DEVICE_CTRL_WDT_SET_TIMEOUT:
90 {
91 RT_ASSERT(*(uint16_t *)args != 0);
92 reload_value = *(uint16_t *)args;
93 // 6.4ms 1 tick, 1s -> 1000 / 6.4 = 625 / 4 ticks
94 reload_value = ((uint32_t)reload_value * 625) / 4;
95 fwdgt_write_enable();
96 while (FWDGT_STAT & FWDGT_STAT_RUD);
97 FWDGT_RLD = FWDGT_RLD_RLD & reload_value;
98 fwdgt_write_disable();
99 }
100 break;
101 case RT_DEVICE_CTRL_WDT_GET_TIMELEFT:
102 *(uint16_t *)args = WDT_RELOAD_SECOND - \
103 (rt_tick_get() - last_tick) / RT_TICK_PER_SECOND;
104
105 break;
106 case RT_DEVICE_CTRL_WDT_KEEPALIVE:
107 {
108 last_tick = rt_tick_get();
109 gd32_wdog_refresh(wdt);
110 }
111 break;
112 case RT_DEVICE_CTRL_WDT_START:
113 {
114 gd32_wdog_open(wdt, *(rt_uint32_t *)args);
115 last_tick = rt_tick_get();
116 wdt_started = 1;
117 while (FWDGT_STAT & FWDGT_STAT_RUD);
118 }
119 break;
120 case RT_DEVICE_CTRL_WDT_STOP:
121 {
122 gd32_wdog_close(wdt);
123 wdt_started = 0;
124 }
125 break;
126 default:
127 return -RT_EINVAL;
128 }
129
130 return RT_EOK;
131 }
132
133 static struct rt_watchdog_ops gd32_wdog_ops =
134 {
135 .init = gd32_wdog_init,
136 .control = gd32_wdog_control,
137 };
138
139 static struct rt_watchdog_device gd32_wdt_device;
140
rt_hw_wdt_init(void)141 int rt_hw_wdt_init(void)
142 {
143 int result = RT_EOK;
144
145 rcu_osci_off(RCU_IRC40K);
146 gd32_wdt_device.ops = &gd32_wdog_ops;
147 result = rt_hw_watchdog_register(&gd32_wdt_device, "wdt", \
148 RT_DEVICE_FLAG_RDWR, (void *)FWDGT);
149
150 return result;
151 }
152
153 INIT_DEVICE_EXPORT(rt_hw_wdt_init);
154
155 #endif /* BSP_USING_WDT */
156
157