1 /**************************************************************************//**
2 *
3 * @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved.
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 *
7 * Change Logs:
8 * Date Author Notes
9 * 2021-6-1 Wayne First version
10 *
11 ******************************************************************************/
12
13 #include <rtthread.h>
14 #include <rtdevice.h>
15 #include "drv_gpio.h"
16 #include "drv_sys.h"
17 #include "drv_sspcc.h"
18
19 #include "board.h"
20
21
22 #if defined(BOARD_USING_STORAGE_SPIFLASH)
23 #if defined(RT_USING_SFUD)
24 #include "dev_spi_flash.h"
25 #include "dev_spi_flash_sfud.h"
26 #endif
27
28 #include "drv_qspi.h"
29
30 #define W25X_REG_READSTATUS (0x05)
31 #define W25X_REG_READSTATUS2 (0x35)
32 #define W25X_REG_WRITEENABLE (0x06)
33 #define W25X_REG_WRITESTATUS (0x01)
34 #define W25X_REG_QUADENABLE (0x02)
35
SpiFlash_ReadStatusReg(struct rt_qspi_device * qspi_device)36 static rt_uint8_t SpiFlash_ReadStatusReg(struct rt_qspi_device *qspi_device)
37 {
38 rt_uint8_t u8Val;
39 rt_err_t result = RT_EOK;
40 rt_uint8_t w25x_txCMD1 = W25X_REG_READSTATUS;
41
42 result = rt_qspi_send_then_recv(qspi_device, &w25x_txCMD1, 1, &u8Val, 1);
43 RT_ASSERT(result > 0);
44
45 return u8Val;
46 }
47
SpiFlash_ReadStatusReg2(struct rt_qspi_device * qspi_device)48 static rt_uint8_t SpiFlash_ReadStatusReg2(struct rt_qspi_device *qspi_device)
49 {
50 rt_uint8_t u8Val;
51 rt_err_t result = RT_EOK;
52 rt_uint8_t w25x_txCMD1 = W25X_REG_READSTATUS2;
53
54 result = rt_qspi_send_then_recv(qspi_device, &w25x_txCMD1, 1, &u8Val, 1);
55 RT_ASSERT(result > 0);
56
57 return u8Val;
58 }
59
SpiFlash_WriteStatusReg(struct rt_qspi_device * qspi_device,uint8_t u8Value1,uint8_t u8Value2)60 static rt_err_t SpiFlash_WriteStatusReg(struct rt_qspi_device *qspi_device, uint8_t u8Value1, uint8_t u8Value2)
61 {
62 rt_uint8_t w25x_txCMD1;
63 rt_uint8_t au8Val[2];
64 rt_err_t result;
65 struct rt_qspi_message qspi_message = {0};
66
67 /* Enable WE */
68 w25x_txCMD1 = W25X_REG_WRITEENABLE;
69 result = rt_qspi_send(qspi_device, &w25x_txCMD1, sizeof(w25x_txCMD1));
70 if (result != sizeof(w25x_txCMD1))
71 goto exit_SpiFlash_WriteStatusReg;
72
73 /* Prepare status-1, 2 data */
74 au8Val[0] = u8Value1;
75 au8Val[1] = u8Value2;
76
77 /* 1-bit mode: Instruction+payload */
78 qspi_message.instruction.content = W25X_REG_WRITESTATUS;
79 qspi_message.instruction.qspi_lines = 1;
80
81 qspi_message.qspi_data_lines = 1;
82 qspi_message.parent.cs_take = 1;
83 qspi_message.parent.cs_release = 1;
84 qspi_message.parent.send_buf = &au8Val[0];
85 qspi_message.parent.length = sizeof(au8Val);
86 qspi_message.parent.next = RT_NULL;
87
88 if (rt_qspi_transfer_message(qspi_device, &qspi_message) != sizeof(au8Val))
89 {
90 result = -RT_ERROR;
91 }
92
93 result = RT_EOK;
94
95 exit_SpiFlash_WriteStatusReg:
96
97 return result;
98 }
99
SpiFlash_WaitReady(struct rt_qspi_device * qspi_device)100 static void SpiFlash_WaitReady(struct rt_qspi_device *qspi_device)
101 {
102 volatile uint8_t u8ReturnValue;
103
104 do
105 {
106 u8ReturnValue = SpiFlash_ReadStatusReg(qspi_device);
107 u8ReturnValue = u8ReturnValue & 1;
108 }
109 while (u8ReturnValue != 0); // check the BUSY bit
110 }
111
SpiFlash_EnterQspiMode(struct rt_qspi_device * qspi_device)112 static void SpiFlash_EnterQspiMode(struct rt_qspi_device *qspi_device)
113 {
114 rt_err_t result = RT_EOK;
115
116 uint8_t u8Status1 = SpiFlash_ReadStatusReg(qspi_device);
117 uint8_t u8Status2 = SpiFlash_ReadStatusReg2(qspi_device);
118
119 u8Status2 |= W25X_REG_QUADENABLE;
120
121 result = SpiFlash_WriteStatusReg(qspi_device, u8Status1, u8Status2);
122 RT_ASSERT(result == RT_EOK);
123
124 SpiFlash_WaitReady(qspi_device);
125 }
126
SpiFlash_ExitQspiMode(struct rt_qspi_device * qspi_device)127 static void SpiFlash_ExitQspiMode(struct rt_qspi_device *qspi_device)
128 {
129 rt_err_t result = RT_EOK;
130 uint8_t u8Status1 = SpiFlash_ReadStatusReg(qspi_device);
131 uint8_t u8Status2 = SpiFlash_ReadStatusReg2(qspi_device);
132
133 u8Status2 &= ~W25X_REG_QUADENABLE;
134
135 result = SpiFlash_WriteStatusReg(qspi_device, u8Status1, u8Status2);
136 RT_ASSERT(result == RT_EOK);
137
138 SpiFlash_WaitReady(qspi_device);
139 }
140
rt_hw_spiflash_init(void)141 static int rt_hw_spiflash_init(void)
142 {
143 if (nu_qspi_bus_attach_device("qspi0", "qspi01", 4, SpiFlash_EnterQspiMode, SpiFlash_ExitQspiMode) != RT_EOK)
144 return -1;
145
146 #if defined(RT_USING_SFUD)
147 if (rt_sfud_flash_probe(FAL_USING_NOR_FLASH_DEV_NAME, "qspi01") == RT_NULL)
148 {
149 return -(RT_ERROR);
150 }
151 #endif
152 return 0;
153 }
154 INIT_DEVICE_EXPORT(rt_hw_spiflash_init);
155 #endif /* BOARD_USING_STORAGE_SPIFLASH */
156
157 #if defined(BOARD_USING_STORAGE_SPINAND) && defined(NU_PKG_USING_SPINAND)
158
159 #include "drv_qspi.h"
160 #include "spinand.h"
161
162 struct rt_mtd_nand_device mtd_partitions[MTD_SPINAND_PARTITION_NUM] =
163 {
164 [0] =
165 {
166 /*nand0: U-boot, env, rtthread*/
167 .block_start = 0,
168 .block_end = 63,
169 .block_total = 64,
170 },
171 [1] =
172 {
173 /*nand1: for filesystem mounting*/
174 .block_start = 64,
175 .block_end = 4095,
176 .block_total = 4032,
177 },
178 [2] =
179 {
180 /*nand2: Whole blocks size, overlay*/
181 .block_start = 0,
182 .block_end = 4095,
183 .block_total = 4096,
184 }
185 };
186
rt_hw_spinand_init(void)187 static int rt_hw_spinand_init(void)
188 {
189 if (nu_qspi_bus_attach_device("qspi0", "qspi01", 4, RT_NULL, RT_NULL) != RT_EOK)
190 return -1;
191
192 if (rt_hw_mtd_spinand_register("qspi01") != RT_EOK)
193 return -1;
194
195 return 0;
196 }
197
198 INIT_DEVICE_EXPORT(rt_hw_spinand_init);
199 #endif
200
201 #if defined(BOARD_USING_MPU6500) && defined(PKG_USING_MPU6XXX)
202
203 #include "sensor_inven_mpu6xxx.h"
204
rt_hw_mpu6xxx_port(void)205 int rt_hw_mpu6xxx_port(void)
206 {
207 struct rt_sensor_config cfg;
208 rt_base_t mpu_int = NU_GET_PININDEX(NU_PL, 8);
209
210 cfg.intf.dev_name = "i2c1";
211 cfg.intf.arg = (void *)MPU6XXX_ADDR_DEFAULT;
212 cfg.irq_pin.pin = mpu_int;
213
214 return rt_hw_mpu6xxx_init("mpu", &cfg);
215 }
216 INIT_APP_EXPORT(rt_hw_mpu6xxx_port);
217 #endif /* BOARD_USING_MPU6500 */
218
219 #if defined(BOARD_USING_STORAGE_RAWNAND) && defined(BSP_USING_NFI)
220 struct rt_mtd_nand_device mtd_partitions_nfi[MTD_NFI_PARTITION_NUM] =
221 {
222 [0] =
223 {
224 /*nand0: rtthread*/
225 .block_start = 0,
226 .block_end = 63,
227 .block_total = 64,
228 },
229 [1] =
230 {
231 /*nand1: for filesystem mounting*/
232 .block_start = 64,
233 .block_end = 8191,
234 .block_total = 8128,
235 },
236 [2] =
237 {
238 /*nand2: Whole blocks size, overlay*/
239 .block_start = 0,
240 .block_end = 8191,
241 .block_total = 8192,
242 }
243 };
244 #endif
245
246 #if defined(BOARD_USING_NAU8822) && defined(NU_PKG_USING_NAU8822)
247 #include <acodec_nau8822.h>
248 S_NU_NAU8822_CONFIG sCodecConfig =
249 {
250 .i2c_bus_name = "i2c2",
251
252 .i2s_bus_name = "sound0",
253
254 .pin_phonejack_en = NU_GET_PININDEX(NU_PD, 13),
255
256 .pin_phonejack_det = NU_GET_PININDEX(NU_PI, 0),
257 };
258
rt_hw_nau8822_port(void)259 int rt_hw_nau8822_port(void)
260 {
261 if (nu_hw_nau8822_init(&sCodecConfig) != RT_EOK)
262 return -1;
263
264 return 0;
265 }
266 INIT_COMPONENT_EXPORT(rt_hw_nau8822_port);
267 #endif /* BOARD_USING_NAU8822 */
268
269 #if defined(NU_PKG_USING_ADC_TOUCH)
270 #include "adc_touch.h"
271 S_CALIBRATION_MATRIX g_sCalMat = { -17558, 1, 69298832, -10, 11142, -2549195, 65536 };
272 #endif
273
274 #if defined(NU_PKG_USING_TPC_GT911) && defined(BOARD_USING_GT911)
275 #include "drv_gpio.h"
276 #include "gt911.h"
277
278 #define TPC_RST_PIN NU_GET_PININDEX(NU_PM, 12)
279 #define TPC_IRQ_PIN NU_GET_PININDEX(NU_PD, 12)
280
281 extern int tpc_sample(const char *name);
rt_hw_gt911_port(void)282 int rt_hw_gt911_port(void)
283 {
284 struct rt_touch_config cfg;
285 rt_uint8_t rst_pin;
286
287 rst_pin = TPC_RST_PIN;
288 cfg.dev_name = "i2c5";
289 cfg.irq_pin.pin = TPC_IRQ_PIN;
290 cfg.irq_pin.mode = PIN_MODE_INPUT_PULLDOWN;
291 cfg.user_data = &rst_pin;
292
293 rt_hw_gt911_init("gt911", &cfg);
294
295 return tpc_sample("gt911");
296 }
297 INIT_ENV_EXPORT(rt_hw_gt911_port);
298 #endif /* if defined(BOARD_USING_GT911) && defined(PKG_USING_GT911) */
299
300 #if defined(BOARD_USING_BUZZER)
301
302 #define EPWM_DEV_NAME "epwm1"
303 #define EPWM_DEV_CHANNEL (5)
304
PlayRingTone(void)305 static void PlayRingTone(void)
306 {
307 struct rt_device_pwm *epwm_dev;
308 rt_uint32_t period;
309 int i, j;
310
311 period = 1000;
312
313 if ((epwm_dev = (struct rt_device_pwm *)rt_device_find(EPWM_DEV_NAME)) != RT_NULL)
314 {
315 rt_pwm_set(epwm_dev, EPWM_DEV_CHANNEL, period, period);
316 rt_pwm_enable(epwm_dev, EPWM_DEV_CHANNEL);
317
318 for (j = 0; j < 5; j++)
319 {
320 for (i = 0; i < 10; i++)
321 {
322 rt_pwm_set(epwm_dev, EPWM_DEV_CHANNEL, period, period);
323 rt_thread_mdelay(50);
324
325 rt_pwm_set(epwm_dev, EPWM_DEV_CHANNEL, period, period / 2);
326 rt_thread_mdelay(50);
327 }
328
329 /* Mute 2 seconds */
330 rt_pwm_set(epwm_dev, EPWM_DEV_CHANNEL, period, period);
331 rt_thread_mdelay(2000);
332 }
333 rt_pwm_disable(epwm_dev, EPWM_DEV_CHANNEL);
334 }
335 else
336 {
337 rt_kprintf("Can't find %s\n", EPWM_DEV_NAME);
338 }
339 }
340
341 #if defined(BOARD_USING_LCM)
342
343 #if defined(PKG_USING_GUIENGINE)
344 #include <rtgui/driver.h>
345 #endif
346
347 #if defined(RT_USING_PIN)
348 #include <drv_gpio.h>
349
350 /* defined the LCM_BLEN pin: PK7 */
351 #define LCM_BACKLIGHT_CTRL NU_GET_PININDEX(NU_PK, 7)
352 #endif
353
354 #define EPWM_DEV_NAME "epwm1"
355 #define LCM_PWM_CHANNEL (1)
356
nu_lcd_backlight_on(void)357 void nu_lcd_backlight_on(void)
358 {
359 struct rt_device_pwm *pwm_dev;
360
361 if ((pwm_dev = (struct rt_device_pwm *)rt_device_find(EPWM_DEV_NAME)) != RT_NULL)
362 {
363 rt_pwm_enable(pwm_dev, LCM_PWM_CHANNEL);
364 rt_pwm_set(pwm_dev, LCM_PWM_CHANNEL, 100000, 100);
365 }
366 else
367 {
368 rt_kprintf("Can't find %s\n", EPWM_DEV_NAME);
369 }
370
371 rt_pin_mode(LCM_BACKLIGHT_CTRL, PIN_MODE_OUTPUT);
372 rt_pin_write(LCM_BACKLIGHT_CTRL, PIN_HIGH);
373 }
374
nu_lcd_backlight_off(void)375 void nu_lcd_backlight_off(void)
376 {
377 struct rt_device_pwm *pwm_dev;
378
379 if ((pwm_dev = (struct rt_device_pwm *)rt_device_find(EPWM_DEV_NAME)) != RT_NULL)
380 {
381 rt_pwm_disable(pwm_dev, LCM_PWM_CHANNEL);
382 }
383 else
384 {
385 rt_kprintf("Can't find %s\n", EPWM_DEV_NAME);
386 }
387
388 rt_pin_mode(LCM_BACKLIGHT_CTRL, PIN_MODE_OUTPUT);
389 rt_pin_write(LCM_BACKLIGHT_CTRL, PIN_LOW);
390 }
391
rt_hw_lcm_port(void)392 int rt_hw_lcm_port(void)
393 {
394 #if defined(PKG_USING_GUIENGINE)
395 rt_device_t lcm_vpost;
396 lcm_vpost = rt_device_find("lcd");
397 if (lcm_vpost)
398 {
399 rtgui_graphic_set_device(lcm_vpost);
400 }
401 #endif
402
403 return 0;
404 }
405 INIT_COMPONENT_EXPORT(rt_hw_lcm_port);
406 #endif /* BOARD_USING_LCM */
407
buzzer_test(void)408 int buzzer_test(void)
409 {
410 PlayRingTone();
411 return 0;
412 }
413 #ifdef FINSH_USING_MSH
414 MSH_CMD_EXPORT(buzzer_test, Buzzer - Play ring tone);
415 #endif
416 #endif /* BOARD_USING_BUZZER */
417
418 #if defined(BOARD_USING_SENSOR0)
419 #include "ccap_sensor.h"
420
421 #define SENSOR0_RST_PIN NU_GET_PININDEX(NU_PM, 1)
422 #define SENSOR0_PD_PIN NU_GET_PININDEX(NU_PK, 8)
423
424 ccap_sensor_io sIo_sensor0 =
425 {
426 .RstPin = SENSOR0_RST_PIN,
427 .PwrDwnPin = SENSOR0_PD_PIN,
428 .I2cName = "i2c3"
429 };
430 #endif /* BOARD_USING_SENSOR0 */
431
432 #if defined(BOARD_USING_SENSOR1)
433 #include "ccap_sensor.h"
434
435 #define SENSOR1_RST_PIN NU_GET_PININDEX(NU_PN, 14)
436 #define SENSOR1_PD_PIN NU_GET_PININDEX(NU_PD, 15)
437
438 ccap_sensor_io sIo_sensor1 =
439 {
440 .RstPin = SENSOR1_RST_PIN,
441 .PwrDwnPin = SENSOR1_PD_PIN,
442 .I2cName = "i2c4"
443 };
444 #endif /* BOARD_USING_SENSOR1 */
445
rt_hw_sensors_port(void)446 int rt_hw_sensors_port(void)
447 {
448 #if defined(BOARD_USING_SENSOR0)
449 nu_ccap_sensor_create(&sIo_sensor0, (ccap_sensor_id)BOARD_USING_SENSON0_ID, "sensor0");
450 #endif
451 #if defined(BOARD_USING_SENSOR1)
452 nu_ccap_sensor_create(&sIo_sensor1, (ccap_sensor_id)BOARD_USING_SENSON1_ID, "sensor1");
453 #endif
454 return 0;
455 }
456 INIT_COMPONENT_EXPORT(rt_hw_sensors_port);
457
458
nu_rtp_sspcc_setup(void)459 void nu_rtp_sspcc_setup(void)
460 {
461 SSPCC_SET_REALM(SSPCC_UART16, SSPCC_SSET_SUBM);
462 SSPCC_SET_REALM(SSPCC_TMR23, SSPCC_SSET_SUBM);
463
464 /* PDMA2/3 */
465 SSPCC_SET_REALM(SSPCC_PDMA2, SSPCC_SSET_SUBM);
466 SSPCC_SET_REALM(SSPCC_PDMA3, SSPCC_SSET_SUBM);
467
468 /* UART16 Pins */
469 SSPCC_SET_GPIO_REALM(PK, 0, SSPCC_SSET_SUBM);
470 SSPCC_SET_GPIO_REALM(PK, 1, SSPCC_SSET_SUBM);
471 SSPCC_SET_GPIO_REALM(PK, 2, SSPCC_SSET_SUBM);
472 SSPCC_SET_GPIO_REALM(PK, 3, SSPCC_SSET_SUBM);
473
474 /* LED_1 Pin */
475 SSPCC_SET_GPIO_REALM(PJ, 15, SSPCC_SSET_SUBM);
476 }
477
478 #define CLK_CLKDIV0_DCUPDIV_2 CLK_CLKDIV0_DCUP(1)
479 #define DISP_FRAMEBUFFERCONFIG0 (DISP_BASE + 0x1518U)
480 #define DISP_OVERLAYCONFIG0 (DISP_BASE + 0x1540U)
481
482 static S_NU_REG s_NuReg_arr[] =
483 {
484 /* DISP PIN */
485 NUREG_EXPORT(SYS_GPH_MFPH, SYS_GPH_MFPH_PH15MFP_Msk, SYS_GPH_MFPH_PH15MFP_LCM_DATA23),
486 NUREG_EXPORT(SYS_GPH_MFPH, SYS_GPH_MFPH_PH14MFP_Msk, SYS_GPH_MFPH_PH14MFP_LCM_DATA22),
487 NUREG_EXPORT(SYS_GPH_MFPH, SYS_GPH_MFPH_PH13MFP_Msk, SYS_GPH_MFPH_PH13MFP_LCM_DATA21),
488 NUREG_EXPORT(SYS_GPH_MFPH, SYS_GPH_MFPH_PH12MFP_Msk, SYS_GPH_MFPH_PH12MFP_LCM_DATA20),
489
490 NUREG_EXPORT(SYS_GPC_MFPH, SYS_GPC_MFPH_PC15MFP_Msk, SYS_GPC_MFPH_PC15MFP_LCM_DATA19),
491 NUREG_EXPORT(SYS_GPC_MFPH, SYS_GPC_MFPH_PC14MFP_Msk, SYS_GPC_MFPH_PC14MFP_LCM_DATA18),
492 NUREG_EXPORT(SYS_GPC_MFPH, SYS_GPC_MFPH_PC13MFP_Msk, SYS_GPC_MFPH_PC13MFP_LCM_DATA17),
493 NUREG_EXPORT(SYS_GPC_MFPH, SYS_GPC_MFPH_PC12MFP_Msk, SYS_GPC_MFPH_PC12MFP_LCM_DATA16),
494
495 NUREG_EXPORT(SYS_GPH_MFPL, SYS_GPH_MFPL_PH7MFP_Msk, SYS_GPH_MFPL_PH7MFP_LCM_DATA15),
496 NUREG_EXPORT(SYS_GPH_MFPL, SYS_GPH_MFPL_PH6MFP_Msk, SYS_GPH_MFPL_PH6MFP_LCM_DATA14),
497 NUREG_EXPORT(SYS_GPH_MFPL, SYS_GPH_MFPL_PH5MFP_Msk, SYS_GPH_MFPL_PH5MFP_LCM_DATA13),
498 NUREG_EXPORT(SYS_GPH_MFPL, SYS_GPH_MFPL_PH4MFP_Msk, SYS_GPH_MFPL_PH4MFP_LCM_DATA12),
499 NUREG_EXPORT(SYS_GPH_MFPL, SYS_GPH_MFPL_PH3MFP_Msk, SYS_GPH_MFPL_PH3MFP_LCM_DATA11),
500 NUREG_EXPORT(SYS_GPH_MFPL, SYS_GPH_MFPL_PH2MFP_Msk, SYS_GPH_MFPL_PH2MFP_LCM_DATA10),
501 NUREG_EXPORT(SYS_GPH_MFPL, SYS_GPH_MFPL_PH1MFP_Msk, SYS_GPH_MFPL_PH1MFP_LCM_DATA9),
502 NUREG_EXPORT(SYS_GPH_MFPL, SYS_GPH_MFPL_PH0MFP_Msk, SYS_GPH_MFPL_PH0MFP_LCM_DATA8),
503
504 NUREG_EXPORT(SYS_GPI_MFPH, SYS_GPI_MFPH_PI15MFP_Msk, SYS_GPI_MFPH_PI15MFP_LCM_DATA7),
505 NUREG_EXPORT(SYS_GPI_MFPH, SYS_GPI_MFPH_PI14MFP_Msk, SYS_GPI_MFPH_PI14MFP_LCM_DATA6),
506 NUREG_EXPORT(SYS_GPI_MFPH, SYS_GPI_MFPH_PI13MFP_Msk, SYS_GPI_MFPH_PI13MFP_LCM_DATA5),
507 NUREG_EXPORT(SYS_GPI_MFPH, SYS_GPI_MFPH_PI12MFP_Msk, SYS_GPI_MFPH_PI12MFP_LCM_DATA4),
508 NUREG_EXPORT(SYS_GPI_MFPH, SYS_GPI_MFPH_PI11MFP_Msk, SYS_GPI_MFPH_PI11MFP_LCM_DATA3),
509 NUREG_EXPORT(SYS_GPI_MFPH, SYS_GPI_MFPH_PI10MFP_Msk, SYS_GPI_MFPH_PI10MFP_LCM_DATA2),
510 NUREG_EXPORT(SYS_GPI_MFPH, SYS_GPI_MFPH_PI9MFP_Msk, SYS_GPI_MFPH_PI9MFP_LCM_DATA1),
511 NUREG_EXPORT(SYS_GPI_MFPH, SYS_GPI_MFPH_PI8MFP_Msk, SYS_GPI_MFPH_PI8MFP_LCM_DATA0),
512
513 NUREG_EXPORT(SYS_GPK_MFPL, SYS_GPK_MFPL_PK4MFP_Msk, SYS_GPK_MFPL_PK4MFP_LCM_DEN),
514
515 NUREG_EXPORT(SYS_GPG_MFPH, SYS_GPG_MFPH_PG10MFP_Msk, SYS_GPG_MFPH_PG10MFP_LCM_CLK),
516 NUREG_EXPORT(SYS_GPG_MFPH, SYS_GPG_MFPH_PG9MFP_Msk, SYS_GPG_MFPH_PG9MFP_LCM_HSYNC),
517 NUREG_EXPORT(SYS_GPG_MFPH, SYS_GPG_MFPH_PG8MFP_Msk, SYS_GPG_MFPH_PG8MFP_LCM_VSYNC),
518
519 /* DISP CLK */
520 NUREG_EXPORT(CLK_SYSCLK0, CLK_SYSCLK0_DCUEN_Msk, CLK_SYSCLK0_DCUEN_Msk),
521
522 /* DISP Engine */
523 NUREG_EXPORT(DISP_FRAMEBUFFERCONFIG0, DISP_FrameBufferConfig0_UNDERFLOW_Msk, DISP_FrameBufferConfig0_UNDERFLOW_Msk),
524 NUREG_EXPORT(DISP_OVERLAYCONFIG0, DISP_OverlayConfig0_UNDERFLOW_Msk, DISP_OverlayConfig0_UNDERFLOW_Msk),
525
526 /* I2C5 */
527 NUREG_EXPORT(SYS_GPJ_MFPH, SYS_GPJ_MFPH_PJ12MFP_Msk, SYS_GPJ_MFPH_PJ12MFP_I2C5_SDA),
528 NUREG_EXPORT(SYS_GPJ_MFPH, SYS_GPJ_MFPH_PJ13MFP_Msk, SYS_GPJ_MFPH_PJ13MFP_I2C5_SCL),
529
530 /* GPD12, PM12 */
531 NUREG_EXPORT(SYS_GPD_MFPH, SYS_GPD_MFPH_PD12MFP_Msk, (0 << SYS_GPD_MFPH_PD12MFP_Pos)),
532 NUREG_EXPORT(SYS_GPM_MFPH, SYS_GPM_MFPH_PM12MFP_Msk, (0 << SYS_GPM_MFPH_PM12MFP_Pos)),
533
534 /* QSPI0 */
535 NUREG_EXPORT(CLK_CLKSEL4, CLK_CLKSEL4_QSPI0SEL_Msk, CLK_CLKSEL4_QSPI0SEL_PCLK0),
536 NUREG_EXPORT(CLK_APBCLK1, CLK_APBCLK1_QSPI0CKEN_Msk, CLK_APBCLK1_QSPI0CKEN_Msk),
537 NUREG_EXPORT(SYS_GPD_MFPL, SYS_GPD_MFPL_PD5MFP_Msk, SYS_GPD_MFPL_PD5MFP_QSPI0_MISO1),
538 NUREG_EXPORT(SYS_GPD_MFPL, SYS_GPD_MFPL_PD4MFP_Msk, SYS_GPD_MFPL_PD4MFP_QSPI0_MOSI1),
539 NUREG_EXPORT(SYS_GPD_MFPL, SYS_GPD_MFPL_PD3MFP_Msk, SYS_GPD_MFPL_PD3MFP_QSPI0_MISO0),
540 NUREG_EXPORT(SYS_GPD_MFPL, SYS_GPD_MFPL_PD2MFP_Msk, SYS_GPD_MFPL_PD2MFP_QSPI0_MOSI0),
541 NUREG_EXPORT(SYS_GPD_MFPL, SYS_GPD_MFPL_PD1MFP_Msk, SYS_GPD_MFPL_PD1MFP_QSPI0_CLK),
542 NUREG_EXPORT(SYS_GPD_MFPL, SYS_GPD_MFPL_PD0MFP_Msk, SYS_GPD_MFPL_PD0MFP_QSPI0_SS0),
543
544 /* TIMERn */
545 NUREG_EXPORT(CLK_APBCLK0, CLK_APBCLK0_TMR0CKEN_Msk, CLK_APBCLK0_TMR0CKEN_Msk),
546 NUREG_EXPORT(CLK_APBCLK0, CLK_APBCLK0_TMR1CKEN_Msk, CLK_APBCLK0_TMR1CKEN_Msk),
547 NUREG_EXPORT(CLK_APBCLK0, CLK_APBCLK0_TMR2CKEN_Msk, CLK_APBCLK0_TMR2CKEN_Msk),
548 NUREG_EXPORT(CLK_APBCLK0, CLK_APBCLK0_TMR3CKEN_Msk, CLK_APBCLK0_TMR3CKEN_Msk),
549 NUREG_EXPORT(CLK_APBCLK0, CLK_APBCLK0_TMR4CKEN_Msk, CLK_APBCLK0_TMR4CKEN_Msk),
550 NUREG_EXPORT(CLK_APBCLK0, CLK_APBCLK0_TMR5CKEN_Msk, CLK_APBCLK0_TMR5CKEN_Msk),
551 NUREG_EXPORT(CLK_APBCLK0, CLK_APBCLK0_TMR6CKEN_Msk, CLK_APBCLK0_TMR6CKEN_Msk),
552 NUREG_EXPORT(CLK_APBCLK0, CLK_APBCLK0_TMR7CKEN_Msk, CLK_APBCLK0_TMR7CKEN_Msk),
553 NUREG_EXPORT(CLK_APBCLK0, CLK_APBCLK0_TMR8CKEN_Msk, CLK_APBCLK0_TMR8CKEN_Msk),
554 NUREG_EXPORT(CLK_APBCLK0, CLK_APBCLK0_TMR9CKEN_Msk, CLK_APBCLK0_TMR9CKEN_Msk),
555 NUREG_EXPORT(CLK_APBCLK0, CLK_APBCLK0_TMR10CKEN_Msk, CLK_APBCLK0_TMR10CKEN_Msk),
556 NUREG_EXPORT(CLK_APBCLK0, CLK_APBCLK0_TMR11CKEN_Msk, CLK_APBCLK0_TMR11CKEN_Msk),
557
558 /* USB Host */
559 NUREG_EXPORT(CLK_SYSCLK0, CLK_SYSCLK0_USBHEN_Msk, CLK_SYSCLK0_USBHEN_Msk),
560 NUREG_EXPORT(CLK_SYSCLK0, CLK_SYSCLK0_HUSBH0EN_Msk, CLK_SYSCLK0_HUSBH0EN_Msk),
561 NUREG_EXPORT(CLK_SYSCLK0, CLK_SYSCLK0_HUSBH1EN_Msk, CLK_SYSCLK0_HUSBH1EN_Msk),
562 NUREG_EXPORT(SYS_USBPMISCR, SYS_USBPMISCR_PHY0SUSPEND_Msk, SYS_USBPMISCR_PHY0SUSPEND_Msk),
563 NUREG_EXPORT(SYS_USBPMISCR, SYS_USBPMISCR_PHY1SUSPEND_Msk, SYS_USBPMISCR_PHY1SUSPEND_Msk),
564 NUREG_EXPORT(SYS_GPL_MFPH, SYS_GPL_MFPH_PL12MFP_Msk, SYS_GPL_MFPH_PL12MFP_HSUSBH_PWREN),
565 NUREG_EXPORT(SYS_GPL_MFPH, SYS_GPL_MFPH_PL13MFP_Msk, SYS_GPL_MFPH_PL13MFP_HSUSBH_OVC),
566
567 /* SDH0 */
568 NUREG_EXPORT(CLK_SYSCLK0, CLK_SYSCLK0_SDH0EN_Msk, CLK_SYSCLK0_SDH0EN_Msk),
569 NUREG_EXPORT(CLK_CLKSEL0, CLK_CLKSEL0_SD0SEL_Msk, CLK_CLKSEL0_SD0SEL_APLL),
570 NUREG_EXPORT(CLK_CLKSEL0, CLK_CLKSEL0_SD0SEL_Msk, CLK_CLKSEL0_SD0SEL_SYSPLL),
571
572 NUREG_EXPORT(SYS_GPC_MFPL, SYS_GPC_MFPL_PC7MFP_Msk, SYS_GPC_MFPL_PC7MFP_SD0_WP),
573 NUREG_EXPORT(SYS_GPC_MFPL, SYS_GPC_MFPL_PC6MFP_Msk, SYS_GPC_MFPL_PC6MFP_SD0_nCD),
574 NUREG_EXPORT(SYS_GPC_MFPL, SYS_GPC_MFPL_PC5MFP_Msk, SYS_GPC_MFPL_PC5MFP_SD0_DAT3),
575 NUREG_EXPORT(SYS_GPC_MFPL, SYS_GPC_MFPL_PC4MFP_Msk, SYS_GPC_MFPL_PC4MFP_SD0_DAT2),
576 NUREG_EXPORT(SYS_GPC_MFPL, SYS_GPC_MFPL_PC3MFP_Msk, SYS_GPC_MFPL_PC3MFP_SD0_DAT1),
577 NUREG_EXPORT(SYS_GPC_MFPL, SYS_GPC_MFPL_PC2MFP_Msk, SYS_GPC_MFPL_PC2MFP_SD0_DAT0),
578 NUREG_EXPORT(SYS_GPC_MFPL, SYS_GPC_MFPL_PC1MFP_Msk, SYS_GPC_MFPL_PC1MFP_SD0_CLK),
579 NUREG_EXPORT(SYS_GPC_MFPL, SYS_GPC_MFPL_PC0MFP_Msk, SYS_GPC_MFPL_PC0MFP_SD0_CMD),
580
581 /* SDH1 */
582 NUREG_EXPORT(CLK_SYSCLK0, CLK_SYSCLK0_SDH1EN_Msk, CLK_SYSCLK0_SDH1EN_Msk),
583 NUREG_EXPORT(CLK_CLKSEL0, CLK_CLKSEL0_SD1SEL_Msk, CLK_CLKSEL0_SD1SEL_APLL),
584 NUREG_EXPORT(CLK_CLKSEL0, CLK_CLKSEL0_SD1SEL_Msk, CLK_CLKSEL0_SD1SEL_SYSPLL),
585
586 NUREG_EXPORT(SYS_GPJ_MFPH, SYS_GPJ_MFPH_PJ11MFP_Msk, SYS_GPJ_MFPH_PJ11MFP_SD1_DAT3),
587 NUREG_EXPORT(SYS_GPJ_MFPH, SYS_GPJ_MFPH_PJ10MFP_Msk, SYS_GPJ_MFPH_PJ10MFP_SD1_DAT2),
588 NUREG_EXPORT(SYS_GPJ_MFPH, SYS_GPJ_MFPH_PJ9MFP_Msk, SYS_GPJ_MFPH_PJ9MFP_SD1_DAT1),
589 NUREG_EXPORT(SYS_GPJ_MFPH, SYS_GPJ_MFPH_PJ8MFP_Msk, SYS_GPJ_MFPH_PJ8MFP_SD1_DAT0),
590 NUREG_EXPORT(SYS_GPJ_MFPL, SYS_GPJ_MFPL_PJ7MFP_Msk, SYS_GPJ_MFPL_PJ7MFP_SD1_CLK),
591 NUREG_EXPORT(SYS_GPJ_MFPL, SYS_GPJ_MFPL_PJ6MFP_Msk, SYS_GPJ_MFPL_PJ6MFP_SD1_CMD),
592 NUREG_EXPORT(SYS_GPJ_MFPL, SYS_GPJ_MFPL_PJ5MFP_Msk, SYS_GPJ_MFPL_PJ5MFP_SD1_nCD),
593 NUREG_EXPORT(SYS_GPJ_MFPL, SYS_GPJ_MFPL_PJ4MFP_Msk, SYS_GPJ_MFPL_PJ4MFP_SD1_WP),
594
595 /* UART11 */
596 NUREG_EXPORT(SYS_GPL_MFPL, SYS_GPL_MFPL_PL0MFP_Msk, SYS_GPL_MFPL_PL0MFP_UART11_nCTS),
597 NUREG_EXPORT(SYS_GPL_MFPL, SYS_GPL_MFPL_PL1MFP_Msk, SYS_GPL_MFPL_PL1MFP_UART11_nRTS),
598 NUREG_EXPORT(SYS_GPL_MFPL, SYS_GPL_MFPL_PL2MFP_Msk, SYS_GPL_MFPL_PL2MFP_UART11_RXD),
599 NUREG_EXPORT(SYS_GPL_MFPL, SYS_GPL_MFPL_PL3MFP_Msk, SYS_GPL_MFPL_PL3MFP_UART11_TXD),
600
601 NUREG_EXPORT(CLK_CLKSEL3, CLK_CLKSEL3_UART11SEL_Msk, CLK_CLKSEL3_UART11SEL_HXT),
602 NUREG_EXPORT(CLK_APBCLK0, CLK_APBCLK0_UART11CKEN_Msk, CLK_APBCLK0_UART11CKEN_Msk),
603
604 /* WDT */
605 NUREG_EXPORT(CLK_CLKSEL3, CLK_CLKSEL3_WDT0SEL_Msk, CLK_CLKSEL3_WDT0SEL_PCLK3_DIV4096),
606
607 /* GMAC0 */
608 NUREG_EXPORT(SYS_GPE_MFPL, SYS_GPE_MFPL_PE0MFP_Msk, SYS_GPE_MFPL_PE0MFP_RGMII0_MDC),
609 NUREG_EXPORT(SYS_GPE_MFPL, SYS_GPE_MFPL_PE1MFP_Msk, SYS_GPE_MFPL_PE1MFP_RGMII0_MDIO),
610 NUREG_EXPORT(SYS_GPE_MFPL, SYS_GPE_MFPL_PE2MFP_Msk, SYS_GPE_MFPL_PE2MFP_RGMII0_TXCTL),
611 NUREG_EXPORT(SYS_GPE_MFPL, SYS_GPE_MFPL_PE3MFP_Msk, SYS_GPE_MFPL_PE3MFP_RGMII0_TXD0),
612 NUREG_EXPORT(SYS_GPE_MFPL, SYS_GPE_MFPL_PE4MFP_Msk, SYS_GPE_MFPL_PE4MFP_RGMII0_TXD1),
613 NUREG_EXPORT(SYS_GPE_MFPL, SYS_GPE_MFPL_PE5MFP_Msk, SYS_GPE_MFPL_PE5MFP_RGMII0_RXCLK),
614 NUREG_EXPORT(SYS_GPE_MFPL, SYS_GPE_MFPL_PE6MFP_Msk, SYS_GPE_MFPL_PE6MFP_RGMII0_RXCTL),
615 NUREG_EXPORT(SYS_GPE_MFPL, SYS_GPE_MFPL_PE7MFP_Msk, SYS_GPE_MFPL_PE7MFP_RGMII0_RXD0),
616 NUREG_EXPORT(SYS_GPE_MFPH, SYS_GPE_MFPH_PE8MFP_Msk, SYS_GPE_MFPH_PE8MFP_RGMII0_RXD1),
617 NUREG_EXPORT(SYS_GPE_MFPH, SYS_GPE_MFPH_PE9MFP_Msk, SYS_GPE_MFPH_PE9MFP_RGMII0_RXD2),
618 NUREG_EXPORT(SYS_GPE_MFPH, SYS_GPE_MFPH_PE10MFP_Msk, SYS_GPE_MFPH_PE10MFP_RGMII0_RXD3),
619 NUREG_EXPORT(SYS_GPE_MFPH, SYS_GPE_MFPH_PE11MFP_Msk, SYS_GPE_MFPH_PE11MFP_RGMII0_TXCLK),
620 NUREG_EXPORT(SYS_GPE_MFPH, SYS_GPE_MFPH_PE12MFP_Msk, SYS_GPE_MFPH_PE12MFP_RGMII0_TXD2),
621 NUREG_EXPORT(SYS_GPE_MFPH, SYS_GPE_MFPH_PE13MFP_Msk, SYS_GPE_MFPH_PE13MFP_RGMII0_TXD3),
622 NUREG_EXPORT(SYS_GPE_MFPH, SYS_GPE_MFPH_PE13MFP_Msk, SYS_GPE_MFPH_PE13MFP_RGMII0_TXD3),
623 NUREG_EXPORT(CLK_SYSCLK0, CLK_SYSCLK0_GMAC0EN_Msk, CLK_SYSCLK0_GMAC0EN_Msk),
624 NUREG_EXPORT(CLK_SYSCLK1, CLK_SYSCLK1_GPECKEN_Msk, CLK_SYSCLK1_GPECKEN_Msk),
625 NUREG_EXPORT(CLK_CLKDIV0, CLK_CLKDIV0_EMAC0DIV_Msk, 0 << CLK_CLKDIV0_EMAC0DIV_Pos), //RGMII
626
627 /* GMAC1 */
628 NUREG_EXPORT(SYS_GPF_MFPL, SYS_GPF_MFPL_PF0MFP_Msk, SYS_GPF_MFPL_PF0MFP_RGMII1_MDC),
629 NUREG_EXPORT(SYS_GPF_MFPL, SYS_GPF_MFPL_PF1MFP_Msk, SYS_GPF_MFPL_PF1MFP_RGMII1_MDIO),
630 NUREG_EXPORT(SYS_GPF_MFPL, SYS_GPF_MFPL_PF2MFP_Msk, SYS_GPF_MFPL_PF2MFP_RGMII1_TXCTL),
631 NUREG_EXPORT(SYS_GPF_MFPL, SYS_GPF_MFPL_PF3MFP_Msk, SYS_GPF_MFPL_PF3MFP_RGMII1_TXD0),
632 NUREG_EXPORT(SYS_GPF_MFPL, SYS_GPF_MFPL_PF4MFP_Msk, SYS_GPF_MFPL_PF4MFP_RGMII1_TXD1),
633 NUREG_EXPORT(SYS_GPF_MFPL, SYS_GPF_MFPL_PF5MFP_Msk, SYS_GPF_MFPL_PF5MFP_RGMII1_RXCLK),
634 NUREG_EXPORT(SYS_GPF_MFPL, SYS_GPF_MFPL_PF6MFP_Msk, SYS_GPF_MFPL_PF6MFP_RGMII1_RXCTL),
635 NUREG_EXPORT(SYS_GPF_MFPL, SYS_GPF_MFPL_PF7MFP_Msk, SYS_GPF_MFPL_PF7MFP_RGMII1_RXD0),
636 NUREG_EXPORT(SYS_GPF_MFPH, SYS_GPF_MFPH_PF8MFP_Msk, SYS_GPF_MFPH_PF8MFP_RGMII1_RXD1),
637 NUREG_EXPORT(SYS_GPF_MFPH, SYS_GPF_MFPH_PF9MFP_Msk, SYS_GPF_MFPH_PF9MFP_RGMII1_RXD2),
638 NUREG_EXPORT(SYS_GPF_MFPH, SYS_GPF_MFPH_PF10MFP_Msk, SYS_GPF_MFPH_PF10MFP_RGMII1_RXD3),
639 NUREG_EXPORT(SYS_GPF_MFPH, SYS_GPF_MFPH_PF11MFP_Msk, SYS_GPF_MFPH_PF11MFP_RGMII1_TXCLK),
640 NUREG_EXPORT(SYS_GPF_MFPH, SYS_GPF_MFPH_PF12MFP_Msk, SYS_GPF_MFPH_PF12MFP_RGMII1_TXD2),
641 NUREG_EXPORT(SYS_GPF_MFPH, SYS_GPF_MFPH_PF13MFP_Msk, SYS_GPF_MFPH_PF13MFP_RGMII1_TXD3),
642 NUREG_EXPORT(CLK_SYSCLK0, CLK_SYSCLK0_GMAC1EN_Msk, CLK_SYSCLK0_GMAC1EN_Msk),
643 NUREG_EXPORT(CLK_SYSCLK1, CLK_SYSCLK1_GPFCKEN_Msk, CLK_SYSCLK1_GPFCKEN_Msk),
644 NUREG_EXPORT(CLK_CLKDIV0, CLK_CLKDIV0_EMAC1DIV_Msk, 0 << CLK_CLKDIV0_EMAC1DIV_Pos), //RGMII
645
646 /* CANFD0 CLK */
647 NUREG_EXPORT(CLK_SYSCLK0, CLK_SYSCLK0_CANFD0CKEN_Msk, CLK_SYSCLK0_CANFD0CKEN_Msk),
648 NUREG_EXPORT(CLK_CLKSEL4, CLK_CLKSEL4_CANFD0SEL_Msk, CLK_CLKSEL4_CANFD0SEL_APLL),
649 NUREG_EXPORT(CLK_CLKDIV0, CLK_CLKDIV0_CANFD0DIV_Msk, CLK_CLKDIV0_CANFD0(1)),
650
651 {0}
652 };
653
nu_check_register(void)654 void nu_check_register(void)
655 {
656 nu_sys_check_register(&s_NuReg_arr[0]);
657 }
658 MSH_CMD_EXPORT(nu_check_register, Check registers);
659