1 /**************************************************************************//**
2 *
3 * @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved.
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 *
7 * Change Logs:
8 * Date Author Notes
9 * 2020-1-16 Wayne First version
10 *
11 ******************************************************************************/
12
13 #include <rtdevice.h>
14 #include <drv_gpio.h>
15
16 #if defined(BOARD_USING_STORAGE_SPIFLASH)
17 #if defined(RT_USING_SFUD)
18 #include "dev_spi_flash.h"
19 #include "dev_spi_flash_sfud.h"
20 #endif
21
22 #include "drv_qspi.h"
23
24 #define W25X_REG_READSTATUS (0x05)
25 #define W25X_REG_READSTATUS2 (0x35)
26 #define W25X_REG_WRITEENABLE (0x06)
27 #define W25X_REG_WRITESTATUS (0x01)
28 #define W25X_REG_QUADENABLE (0x02)
29
SpiFlash_ReadStatusReg(struct rt_qspi_device * qspi_device)30 static rt_uint8_t SpiFlash_ReadStatusReg(struct rt_qspi_device *qspi_device)
31 {
32 rt_uint8_t u8Val;
33 rt_err_t result = RT_EOK;
34 rt_uint8_t w25x_txCMD1 = W25X_REG_READSTATUS;
35
36 result = rt_qspi_send_then_recv(qspi_device, &w25x_txCMD1, 1, &u8Val, 1);
37 RT_ASSERT(result > 0);
38
39 return u8Val;
40 }
41
SpiFlash_ReadStatusReg2(struct rt_qspi_device * qspi_device)42 static rt_uint8_t SpiFlash_ReadStatusReg2(struct rt_qspi_device *qspi_device)
43 {
44 rt_uint8_t u8Val;
45 rt_err_t result = RT_EOK;
46 rt_uint8_t w25x_txCMD1 = W25X_REG_READSTATUS2;
47
48 result = rt_qspi_send_then_recv(qspi_device, &w25x_txCMD1, 1, &u8Val, 1);
49 RT_ASSERT(result > 0);
50
51 return u8Val;
52 }
53
SpiFlash_WriteStatusReg(struct rt_qspi_device * qspi_device,uint8_t u8Value1,uint8_t u8Value2)54 static rt_err_t SpiFlash_WriteStatusReg(struct rt_qspi_device *qspi_device, uint8_t u8Value1, uint8_t u8Value2)
55 {
56 rt_uint8_t w25x_txCMD1;
57 rt_uint8_t au8Val[2];
58 rt_err_t result;
59 struct rt_qspi_message qspi_message = {0};
60
61 /* Enable WE */
62 w25x_txCMD1 = W25X_REG_WRITEENABLE;
63 result = rt_qspi_send(qspi_device, &w25x_txCMD1, sizeof(w25x_txCMD1));
64 if (result != sizeof(w25x_txCMD1))
65 goto exit_SpiFlash_WriteStatusReg;
66
67 /* Prepare status-1, 2 data */
68 au8Val[0] = u8Value1;
69 au8Val[1] = u8Value2;
70
71 /* 1-bit mode: Instruction+payload */
72 qspi_message.instruction.content = W25X_REG_WRITESTATUS;
73 qspi_message.instruction.qspi_lines = 1;
74
75 qspi_message.qspi_data_lines = 1;
76 qspi_message.parent.cs_take = 1;
77 qspi_message.parent.cs_release = 1;
78 qspi_message.parent.send_buf = &au8Val[0];
79 qspi_message.parent.length = sizeof(au8Val);
80 qspi_message.parent.next = RT_NULL;
81
82 if (rt_qspi_transfer_message(qspi_device, &qspi_message) != sizeof(au8Val))
83 {
84 result = -RT_ERROR;
85 }
86
87 result = RT_EOK;
88
89 exit_SpiFlash_WriteStatusReg:
90
91 return result;
92 }
93
SpiFlash_WaitReady(struct rt_qspi_device * qspi_device)94 static void SpiFlash_WaitReady(struct rt_qspi_device *qspi_device)
95 {
96 volatile uint8_t u8ReturnValue;
97
98 do
99 {
100 u8ReturnValue = SpiFlash_ReadStatusReg(qspi_device);
101 u8ReturnValue = u8ReturnValue & 1;
102 }
103 while (u8ReturnValue != 0); // check the BUSY bit
104 }
105
SpiFlash_EnterQspiMode(struct rt_qspi_device * qspi_device)106 static void SpiFlash_EnterQspiMode(struct rt_qspi_device *qspi_device)
107 {
108 rt_err_t result = RT_EOK;
109
110 uint8_t u8Status1 = SpiFlash_ReadStatusReg(qspi_device);
111 uint8_t u8Status2 = SpiFlash_ReadStatusReg2(qspi_device);
112
113 u8Status2 |= W25X_REG_QUADENABLE;
114
115 result = SpiFlash_WriteStatusReg(qspi_device, u8Status1, u8Status2);
116 RT_ASSERT(result == RT_EOK);
117
118 SpiFlash_WaitReady(qspi_device);
119 }
120
SpiFlash_ExitQspiMode(struct rt_qspi_device * qspi_device)121 static void SpiFlash_ExitQspiMode(struct rt_qspi_device *qspi_device)
122 {
123 rt_err_t result = RT_EOK;
124 uint8_t u8Status1 = SpiFlash_ReadStatusReg(qspi_device);
125 uint8_t u8Status2 = SpiFlash_ReadStatusReg2(qspi_device);
126
127 u8Status2 &= ~W25X_REG_QUADENABLE;
128
129 result = SpiFlash_WriteStatusReg(qspi_device, u8Status1, u8Status2);
130 RT_ASSERT(result == RT_EOK);
131
132 SpiFlash_WaitReady(qspi_device);
133 }
134
rt_hw_spiflash_init(void)135 static int rt_hw_spiflash_init(void)
136 {
137 /* Here, we use Dual I/O to drive the SPI flash by default. */
138 /* If you want to use Quad I/O, you can modify to 4 from 2 and crossover D2/D3 pin of SPI flash. */
139 if (nu_qspi_bus_attach_device("qspi0", "qspi01", 2, SpiFlash_EnterQspiMode, SpiFlash_ExitQspiMode) != RT_EOK)
140 return -1;
141
142 #if defined(RT_USING_SFUD)
143 if (rt_sfud_flash_probe("flash0", "qspi01") == RT_NULL)
144 {
145 return -(RT_ERROR);
146 }
147 #endif
148 return 0;
149 }
150 INIT_COMPONENT_EXPORT(rt_hw_spiflash_init);
151 #endif /* BOARD_USING_STORAGE_SPIFLASH */
152
153 #if defined(BOARD_USING_SRAM0_AS_MEMHEAP)
154 /*
155 In Advance board design, SRAM address bus A16/A17/A18 are GPIO-controlled by SW, not EBI.
156 So we just remap 128KB only to RTT memory heap, due to it is out of control.
157 AD0~AD15: 2^16*16bit = 128KB
158 */
159 #include <drv_ebi.h>
160 #include "NuMicro.h"
161 static struct rt_memheap system_heap;
nu_use_exsram_as_heap(void)162 int nu_use_exsram_as_heap(void)
163 {
164 rt_err_t ret;
165
166 /* Open ebi bank1 */
167 ret = nu_ebi_init(EBI_BANK1, EBI_BUSWIDTH_16BIT, EBI_TIMING_SLOWEST, EBI_OPMODE_NORMAL, EBI_CS_ACTIVE_LOW);
168 if (ret != RT_EOK)
169 return ret;
170
171 /* Initial sram as heap */
172 return rt_memheap_init(&system_heap, "nu_sram_heap", (void *)EBI_BANK1_BASE_ADDR, 128 * 1024);
173 }
174 INIT_BOARD_EXPORT(nu_use_exsram_as_heap);
175 #endif /* BOARD_USING_SRAM0_AS_MEMHEAP */
176
177
178 #if defined(BOARD_USING_MAX31875)
179 #include <sensor_max31875.h>
rt_hw_max31875_port(void)180 int rt_hw_max31875_port(void)
181 {
182 struct rt_sensor_config cfg;
183
184 cfg.intf.dev_name = "i2c1";
185 cfg.intf.arg = (void *)MAX31875_I2C_SLAVE_ADR_R0;
186 cfg.irq_pin.pin = PIN_IRQ_PIN_NONE;
187
188 rt_hw_max31875_init("max31875", &cfg);
189 return 0;
190 }
191 INIT_APP_EXPORT(rt_hw_max31875_port);
192 #endif /* BOARD_USING_MAX31875 */
193
194 #if defined(BOARD_USING_MPU6500)
195 #include <sensor_inven_mpu6xxx.h>
rt_hw_mpu6500_port(void)196 int rt_hw_mpu6500_port(void)
197 {
198 struct rt_sensor_config cfg;
199
200 cfg.intf.dev_name = "i2c2";
201 cfg.intf.arg = (void *)MPU6XXX_ADDR_DEFAULT;
202 cfg.irq_pin.pin = PIN_IRQ_PIN_NONE;
203
204 rt_hw_mpu6xxx_init("mpu", &cfg);
205 return 0;
206 }
207 INIT_APP_EXPORT(rt_hw_mpu6500_port);
208 #endif /* BOARD_USING_MPU6500 */
209
210 #if defined(BOARD_USING_LCD_ILI9341) && defined(NU_PKG_USING_ILI9341_EBI)
211
212 #if defined(NU_PKG_USING_ADC_TOUCH_SW)
213
214 #include "adc_touch.h"
215 #include "touch_sw.h"
216
217 #define NU_MFP_POS(PIN) ((PIN % 8) * 4)
218 #define NU_MFP_MSK(PIN) (0xful << NU_MFP_POS(PIN))
219
220 S_CALIBRATION_MATRIX g_sCalMat = { -7, 6358, -3727548, 4990, 30, -2368560, 65536 };
221
nu_pin_func(rt_base_t pin,int data)222 static void nu_pin_func(rt_base_t pin, int data)
223 {
224 uint32_t pin_index = NU_GET_PINS(pin);
225 uint32_t port_index = NU_GET_PORT(pin);
226 __IO uint32_t *GPx_MFPx = ((__IO uint32_t *) &SYS->GPA_MFPL) + port_index * 2 + (pin_index / 8);
227 uint32_t MFP_Msk = NU_MFP_MSK(pin_index);
228
229 *GPx_MFPx = (*GPx_MFPx & (~MFP_Msk)) | data;
230 }
231
tp_switch_to_analog(rt_base_t pin)232 static void tp_switch_to_analog(rt_base_t pin)
233 {
234 GPIO_T *port = (GPIO_T *)(GPIOA_BASE + (0x40) * NU_GET_PORT(pin));
235
236 if (pin == NU_GET_PININDEX(NU_PB, 8))
237 nu_pin_func(pin, SYS_GPB_MFPH_PB8MFP_EADC0_CH8);
238 else if (pin == NU_GET_PININDEX(NU_PB, 9))
239 nu_pin_func(pin, SYS_GPB_MFPH_PB9MFP_EADC0_CH9);
240
241 GPIO_DISABLE_DIGITAL_PATH(port, NU_GET_PIN_MASK(NU_GET_PINS(pin)));
242 }
243
tp_switch_to_digital(rt_base_t pin)244 static void tp_switch_to_digital(rt_base_t pin)
245 {
246 GPIO_T *port = (GPIO_T *)(GPIOA_BASE + (0x40) * NU_GET_PORT(pin));
247
248 nu_pin_func(pin, 0);
249
250 /* Enable digital path on these EADC pins */
251 GPIO_ENABLE_DIGITAL_PATH(port, NU_GET_PIN_MASK(NU_GET_PINS(pin)));
252 }
253
254 static S_TOUCH_SW sADCTP =
255 {
256 .adc_name = "eadc0",
257 .i32ADCChnYU = 8,
258 .i32ADCChnXR = 9,
259 .pin =
260 {
261 NU_GET_PININDEX(NU_PH, 4), // XL
262 NU_GET_PININDEX(NU_PB, 8), // YU
263 NU_GET_PININDEX(NU_PB, 9), // XR
264 NU_GET_PININDEX(NU_PH, 5), // YD
265 },
266 .switch_to_analog = tp_switch_to_analog,
267 .switch_to_digital = tp_switch_to_digital,
268 };
269 #endif
270
271
272 #include <lcd_ili9341.h>
273 #if defined(PKG_USING_GUIENGINE)
274 #include <rtgui/driver.h>
275 #endif
rt_hw_ili9341_port(void)276 int rt_hw_ili9341_port(void)
277 {
278 rt_err_t ret = RT_EOK;
279
280 /* Open ebi BOARD_USING_ILI9341_EBI_PORT */
281 ret = nu_ebi_init(BOARD_USING_ILI9341_EBI_PORT, EBI_BUSWIDTH_16BIT, EBI_TIMING_NORMAL, EBI_OPMODE_NORMAL, EBI_CS_ACTIVE_LOW);
282 if (ret != RT_EOK)
283 return ret;
284
285 switch (BOARD_USING_ILI9341_EBI_PORT)
286 {
287 case 0:
288 EBI->CTL0 |= EBI_CTL0_CACCESS_Msk;
289 EBI->TCTL0 |= (EBI_TCTL0_WAHDOFF_Msk | EBI_TCTL0_RAHDOFF_Msk);
290 break;
291 case 1:
292 EBI->CTL1 |= EBI_CTL1_CACCESS_Msk;
293 EBI->TCTL1 |= (EBI_TCTL1_WAHDOFF_Msk | EBI_TCTL1_RAHDOFF_Msk);
294 break;
295 case 2:
296 EBI->CTL2 |= EBI_CTL2_CACCESS_Msk;
297 EBI->TCTL2 |= (EBI_TCTL2_WAHDOFF_Msk | EBI_TCTL2_RAHDOFF_Msk);
298 break;
299 default:
300 return -1;
301 }
302
303 if (rt_hw_lcd_ili9341_ebi_init(EBI_BANK0_BASE_ADDR + BOARD_USING_ILI9341_EBI_PORT * EBI_MAX_SIZE) != RT_EOK)
304 return -1;
305
306 rt_hw_lcd_ili9341_init();
307
308 #if defined(PKG_USING_GUIENGINE)
309 rt_device_t lcd_ili9341;
310 lcd_ili9341 = rt_device_find("lcd");
311 if (lcd_ili9341)
312 {
313 rtgui_graphic_set_device(lcd_ili9341);
314 }
315 #endif
316
317 #if defined(NU_PKG_USING_ADC_TOUCH_SW)
318 nu_adc_touch_sw_register(&sADCTP);
319 #endif
320
321 return 0;
322 }
323 INIT_COMPONENT_EXPORT(rt_hw_ili9341_port);
324 #endif /* BOARD_USING_LCD_ILI9341 */
325
326 #if defined(BOARD_USING_NAU88L25) && defined(NU_PKG_USING_NAU88L25)
327 #include <acodec_nau88l25.h>
328 S_NU_NAU88L25_CONFIG sCodecConfig =
329 {
330 .i2c_bus_name = "i2c2",
331
332 .i2s_bus_name = "sound0",
333
334 .pin_phonejack_en = NU_GET_PININDEX(NU_PE, 13),
335
336 .pin_phonejack_det = 0,
337 };
338
rt_hw_nau88l25_port(void)339 int rt_hw_nau88l25_port(void)
340 {
341 if (nu_hw_nau88l25_init(&sCodecConfig) != RT_EOK)
342 return -1;
343
344 return 0;
345 }
346 INIT_COMPONENT_EXPORT(rt_hw_nau88l25_port);
347 #endif /* BOARD_USING_NAU88L25 */
348
349 #if defined(BOARD_USING_BUZZER)
350
351 #define BPWM_DEV_NAME "bpwm0"
352 #define BPWM_DEV_CHANNEL (5)
353
PlayRingTone(void)354 static void PlayRingTone(void)
355 {
356 struct rt_device_pwm *bpwm_dev;
357 rt_uint32_t period;
358 int i, j;
359
360 period = 1000;
361
362 if ((bpwm_dev = (struct rt_device_pwm *)rt_device_find(BPWM_DEV_NAME)) != RT_NULL)
363 {
364 rt_pwm_set(bpwm_dev, BPWM_DEV_CHANNEL, period, period);
365 rt_pwm_enable(bpwm_dev, BPWM_DEV_CHANNEL);
366
367 for (j = 0; j < 5; j++)
368 {
369 for (i = 0; i < 10; i++)
370 {
371 rt_pwm_set(bpwm_dev, BPWM_DEV_CHANNEL, period, period);
372 rt_thread_mdelay(50);
373
374 rt_pwm_set(bpwm_dev, BPWM_DEV_CHANNEL, period, period / 2);
375 rt_thread_mdelay(50);
376 }
377
378 /* Mute 2 seconds */
379 rt_pwm_set(bpwm_dev, BPWM_DEV_CHANNEL, period, period);
380 rt_thread_mdelay(2000);
381 }
382 rt_pwm_disable(bpwm_dev, BPWM_DEV_CHANNEL);
383 }
384 else
385 {
386 rt_kprintf("Can't find %s\n", BPWM_DEV_NAME);
387 }
388 }
389
buzzer_test(void)390 int buzzer_test(void)
391 {
392 PlayRingTone();
393 return 0;
394 }
395 #ifdef FINSH_USING_MSH
396 MSH_CMD_EXPORT(buzzer_test, Buzzer - Play ring tone);
397 #endif
398 #endif /* BOARD_USING_BUZZER */
399