1 /******************************************************************************
2 * @brief providing common gpio API.
3 *
4 ******************************************************************************/
5 #include "gpio.h"
6
7 /******************************************************************************
8 * Local variables
9 ******************************************************************************/
10
11
12 /******************************************************************************
13 * Local function prototypes
14 ******************************************************************************/
15
16 /******************************************************************************
17 * Local functions
18 *****************************************************************************/
19
20 /******************************************************************************
21 * Global functions
22 ******************************************************************************/
23
24 /******************************************************************************
25 * define GPIO APIs
26 *
27 *//*! @addtogroup gpio_api_list
28 * @{
29 *******************************************************************************/
30
31 /*****************************************************************************//*!
32 * @brief Initialize the GPIO registers to the default reset values.
33 *
34 * @param[in] pGPIO Pointer to GPIO module, can be GPIOA/GPIOB.
35 *
36 * @return none
37 *
38 * @ Pass/ Fail criteria: none
39 *****************************************************************************/
GPIO_DeInit(GPIO_Type * pGPIO)40 void GPIO_DeInit(GPIO_Type *pGPIO)
41 {
42 /* Sanity check */
43 #if defined(CPU_NV32)
44 ASSERT((pGPIO == GPIOA) || (pGPIO == GPIOB));
45 #endif
46 #if defined(CPU_NV32M3)
47 ASSERT(pGPIO == GPIOA);
48 #endif
49 #if defined(CPU_NV32M4)
50 ASSERT((pGPIO == GPIOA) || (pGPIO == GPIOB) || (pGPIO == GPIOC));
51 #endif
52
53 pGPIO->PCOR = 0x00000000; /* Port Clear Output Register */
54 pGPIO->PDDR = 0x00000000; /* Port Data Direction */
55 //pGPIO->PDIR = 0x00000000; /* Port Data Input Register */
56 pGPIO->PDOR = 0x00000000; /* Port Data Output Register */
57 pGPIO->PIDR = 0xFFFFFFFF; /* Port Input Disable Register */
58 pGPIO->PSOR = 0x00000000; /* Port Set Output Register */
59 pGPIO->PTOR = 0x00000000; /* Port Toggle Output Register */
60 }
61
62 /*****************************************************************************//*!
63 * @brief Initialize GPIO pins which are specified by u32PinMask
64 *
65 * @param[in] pGPIO Pointer to GPIO module, can be GPIOA/GPIOB.
66 * @param[in] u32PinMask GPIO pin mask need to be set
67 * @param[in] sGpioType pin attribute
68 *
69 * @return none
70 *
71 * @Note
72 * . High-current drive function is disabled, if the pin is configured as an input
73 * . Internal pullup is disabled if the pin is configured as an output
74 *
75 * @ Pass/ Fail criteria: none
76 *****************************************************************************/
GPIO_Init(GPIO_Type * pGPIO,uint32_t u32PinMask,GPIO_PinConfigType sGpioType)77 void GPIO_Init(GPIO_Type *pGPIO, uint32_t u32PinMask, GPIO_PinConfigType sGpioType)
78 {
79 /* Sanity check */
80 #if defined(CPU_NV32)
81 ASSERT((pGPIO == GPIOA) || (pGPIO == GPIOB));
82 #endif
83 #if defined(CPU_NV32M3)
84 ASSERT(pGPIO == GPIOA);
85 #endif
86 #if defined(CPU_NV32M4)
87 ASSERT((pGPIO == GPIOA) || (pGPIO == GPIOB) || (pGPIO == GPIOC));
88 #endif
89
90 /* Config GPIO for Input or Output */
91 if ((sGpioType == GPIO_PinOutput) || (sGpioType == GPIO_PinOutput_HighCurrent))
92 {
93 pGPIO->PDDR |= u32PinMask; /* Enable Port Data Direction Register */
94 pGPIO->PIDR |= u32PinMask; /* Set Port Input Disable Register */
95 }
96 else if ((sGpioType == GPIO_PinInput) || (sGpioType == GPIO_PinInput_InternalPullup))
97 {
98 pGPIO->PDDR &= ~u32PinMask; /* Disable Port Data Direction Register */
99 pGPIO->PIDR &= ~u32PinMask; /* Clear Port Input Disable Register */
100 }
101 /* Config PORT Pull select for GPIO */
102 #if defined(CPU_NV32)
103 switch((uint32_t)pGPIO)
104 {
105 case GPIOA_BASE:
106 (sGpioType == GPIO_PinInput_InternalPullup)?(PORT->PUEL |= u32PinMask):(PORT->PUEL &= ~u32PinMask);
107 break;
108 case GPIOB_BASE:
109 (sGpioType == GPIO_PinInput_InternalPullup)?(PORT->PUEH |= u32PinMask):(PORT->PUEH &= ~u32PinMask);
110 break;
111 default:
112 break;
113 }
114 #endif
115
116 #if defined(CPU_NV32M3)
117 switch((uint32_t)pGPIO)
118 {
119 case GPIOA_BASE:
120 (sGpioType == GPIO_PinInput_InternalPullup)?(PORT->PUEL |= u32PinMask):(PORT->PUEL &= ~u32PinMask);
121 break;
122 default:
123 break;
124 }
125 #endif
126
127 #if defined(CPU_NV32M4)
128 switch((uint32_t)pGPIO)
129 {
130 case GPIOA_BASE:
131 (sGpioType == GPIO_PinInput_InternalPullup)?(PORT->PUE0 |= u32PinMask):(PORT->PUE0 &= ~u32PinMask);
132 break;
133 case GPIOB_BASE:
134 (sGpioType == GPIO_PinInput_InternalPullup)?(PORT->PUE1 |= u32PinMask):(PORT->PUE1 &= ~u32PinMask);
135 break;
136 case GPIOC_BASE:
137 (sGpioType == GPIO_PinInput_InternalPullup)?(PORT->PUE2 |= u32PinMask):(PORT->PUE2 &= ~u32PinMask);
138 break;
139 default:
140 break;
141 }
142 #endif
143
144 /* Config PORT GPIO_PinOutput_HighCurrent for GPIO */
145 #if defined(CPU_NV32M3)
146 if (u32PinMask & GPIO_PTC5_MASK)
147 {
148 PORT->HDRVE |= PORT_HDRVE_PTC5_MASK;
149 }
150 if (u32PinMask & GPIO_PTC1_MASK)
151 {
152 PORT->HDRVE |= PORT_HDRVE_PTC1_MASK;
153 }
154 if (u32PinMask & GPIO_PTB5_MASK)
155 {
156 PORT->HDRVE |= PORT_HDRVE_PTB5_MASK;
157 }
158 #endif
159
160 #if defined(CPU_NV32) | defined(CPU_NV32M4)
161 if (pGPIO == GPIOA)
162 {
163 if (u32PinMask & GPIO_PTB4_MASK)
164 {
165 PORT->HDRVE |= PORT_HDRVE_PTB4_MASK;
166 }
167 if (u32PinMask & GPIO_PTB5_MASK)
168 {
169 PORT->HDRVE |= PORT_HDRVE_PTB5_MASK;
170 }
171 if (u32PinMask & GPIO_PTD0_MASK)
172 {
173 PORT->HDRVE |= PORT_HDRVE_PTD0_MASK;
174 }
175 if (u32PinMask & GPIO_PTD1_MASK)
176 {
177 PORT->HDRVE |= PORT_HDRVE_PTD1_MASK;
178 }
179 }
180 if (pGPIO == GPIOB)
181 {
182 if (u32PinMask & GPIO_PTE0_MASK)
183 {
184 PORT->HDRVE |= PORT_HDRVE_PTE0_MASK;
185 }
186 if (u32PinMask & GPIO_PTE1_MASK)
187 {
188 PORT->HDRVE |= PORT_HDRVE_PTE1_MASK;
189 }
190 if (u32PinMask & GPIO_PTH0_MASK)
191 {
192 PORT->HDRVE |= PORT_HDRVE_PTH0_MASK;
193 }
194 if (u32PinMask & GPIO_PTH1_MASK)
195 {
196 PORT->HDRVE |= PORT_HDRVE_PTH1_MASK;
197 }
198 }
199
200 #endif
201
202 }
203
204
205
206 /*****************************************************************************//*!
207 * @brief Toggle the pins which are specified by u32PinMask
208 *
209 * @param[in] pGPIO Pointer to GPIO module, can be GPIOA/GPIOB.
210 * @param[in] u32PinMask Specify GPIO pin need to be toggled
211 *
212 * @return none
213 *
214 * @ Pass/ Fail criteria: none
215 *****************************************************************************/
GPIO_Toggle(GPIO_Type * pGPIO,uint32_t u32PinMask)216 void GPIO_Toggle(GPIO_Type *pGPIO, uint32_t u32PinMask)
217 {
218 /* Sanity check */
219 #if defined(CPU_NV32)
220 ASSERT((pGPIO == GPIOA) || (pGPIO == GPIOB));
221 #endif
222 #if defined(CPU_NV32M3)
223 ASSERT(pGPIO == GPIOA);
224 #endif
225 #if defined(CPU_NV32M4)
226 ASSERT((pGPIO == GPIOA) || (pGPIO == GPIOB) || (pGPIO == GPIOC));
227 #endif
228
229 pGPIO->PTOR = u32PinMask; /* Toggle the pins specified by u32PinMask */
230 }
231
232 /*****************************************************************************//*!
233 * @brief Read input data from GPIO which is specified by pGPIO
234 *
235 * @param[in] pGPIO Pointer to GPIO module, can be GPIOA/GPIOB.
236 *
237 * @return GPIO input value unsigned int 32-bit
238 *
239 * @ Pass/ Fail criteria: none
240 *****************************************************************************/
GPIO_Read(GPIO_Type * pGPIO)241 uint32_t GPIO_Read(GPIO_Type *pGPIO)
242 {
243 /* Sanity check */
244 #if defined(CPU_NV32)
245 ASSERT((pGPIO == GPIOA) || (pGPIO == GPIOB));
246 #endif
247 #if defined(CPU_NV32M3)
248 ASSERT(pGPIO == GPIOA);
249 #endif
250 #if defined(CPU_NV32M4)
251 ASSERT((pGPIO == GPIOA) || (pGPIO == GPIOB) || (pGPIO == GPIOC));
252 #endif
253
254 return (pGPIO->PDIR); /* Read Port Data Input Register */
255
256 }
257
258 /*****************************************************************************//*!
259 * @brief Read input data from Bit GPIO which is specified by pGPIO
260 *
261 * @param[in] pGPIO Pointer to GPIO module, can be GPIOA/GPIOB.
262 *
263 * @return Bit GPIO input value
264 *
265 * @ Pass/ Fail criteria: none
266 *****************************************************************************/
GPIO_BitRead(GPIO_PinType GPIO_Pin)267 uint8_t GPIO_BitRead(GPIO_PinType GPIO_Pin)
268 {
269 uint8_t data;
270 /* Sanity check */
271 ASSERT(GPIO_Pin <= GPIO_PTI7);
272
273
274 /* Config GPIO and pull select*/
275
276 if (GPIO_Pin < GPIO_PTE0)
277 {
278 if(((1<<GPIO_Pin) & GPIOA->PDIR) > 0) /* Read Bit GPIO input value */
279 data = 0x1; /* return value */
280 else
281 data = 0x0;
282
283 }
284
285 else if (GPIO_Pin < GPIO_PTI0)
286 {
287 GPIO_Pin = (GPIO_PinType)(GPIO_Pin - 32);
288
289 if(((1<<GPIO_Pin) & GPIOB->PDIR) > 0) /* Read Bit GPIO input value */
290 data = 0x1; /* return value */
291 else
292 data = 0x0;
293
294 }
295
296 return data;
297
298 }
299
300
301 /*****************************************************************************//*!
302 * @brief Write output data to GPIO which is specified by pGPIO
303 *
304 * @param[in] pGPIO Pointer to GPIO module, can be GPIOA/GPIOB.
305 * @param[in] u32Value value to output
306 *
307 * @return none
308 *
309 * @ Pass/ Fail criteria: none
310 *****************************************************************************/
GPIO_Write(GPIO_Type * pGPIO,uint32_t u32Value)311 void GPIO_Write(GPIO_Type *pGPIO, uint32_t u32Value)
312 {
313 /* Sanity check */
314 #if defined(CPU_NV32)
315 ASSERT((pGPIO == GPIOA) || (pGPIO == GPIOB));
316 #endif
317 #if defined(CPU_NV32M3)
318 ASSERT(pGPIO == GPIOA);
319 #endif
320 #if defined(CPU_NV32M4)
321 ASSERT((pGPIO == GPIOA) || (pGPIO == GPIOB) || (pGPIO == GPIOC));
322 #endif
323
324 pGPIO->PDOR = u32Value; /* Write Port Ouput Data Register */
325
326 }
327
328 /*****************************************************************************//*!
329 * @brief Initialize GPIO single pin which is specified by GPIO_Pin
330 *
331 * @param[in] GPIO_Pin GPIO pin name, can be GPIO_PTA0,1 ...
332 * @param[in] GPIO_PinConfig Config output or input
333 *
334 * @return none
335 *
336 * @ Pass/ Fail criteria: none
337 *****************************************************************************/
GPIO_PinInit(GPIO_PinType GPIO_Pin,GPIO_PinConfigType GPIO_PinConfig)338 void GPIO_PinInit(GPIO_PinType GPIO_Pin, GPIO_PinConfigType GPIO_PinConfig)
339 {
340 /* Sanity check */
341 ASSERT(GPIO_Pin <= GPIO_PTI7);
342
343 /* Config GPIO and pull select*/
344 #if defined(CPU_NV32)
345 if (GPIO_Pin < GPIO_PTE0)
346 {
347 switch (GPIO_PinConfig)
348 {
349 case GPIO_PinOutput:
350 GPIOA->PDDR |= (1<<GPIO_Pin); /* Enable Port Data Direction Register */
351 GPIOA->PIDR |= (1<<GPIO_Pin); /* Set Port Input Disable Register */
352 PORT->PUEL &= ~(1<<GPIO_Pin); /* Disable Pullup */
353 break;
354 case GPIO_PinInput:
355 GPIOA->PDDR &= ~(1<<GPIO_Pin); /* Disable Port Data Direction Register */
356 GPIOA->PIDR &= ~(1<<GPIO_Pin); /* Clear Port Input Disable Register */
357 PORT->PUEL &= ~(1<<GPIO_Pin); /* Disable Pullup */
358 break;
359 case GPIO_PinInput_InternalPullup:
360 GPIOA->PDDR &= ~(1<<GPIO_Pin); /* Disable Port Data Direction Register */
361 GPIOA->PIDR &= ~(1<<GPIO_Pin); /* Clear Port Input Disable Register */
362 PORT->PUEL |= (1<<GPIO_Pin); /* Enable Pullup */
363 break;
364 case GPIO_PinOutput_HighCurrent:
365 GPIOA->PDDR |= (1<<GPIO_Pin); /* Enable Port Data Direction Register */
366 GPIOA->PIDR |= (1<<GPIO_Pin); /* Set Port Input Disable Register */
367 PORT->PUEL &= ~(1<<GPIO_Pin); /* Disable Pullup */
368 break;
369 }
370 }
371 else if (GPIO_Pin < GPIO_PTI0)
372 {
373 GPIO_Pin = (GPIO_PinType)(GPIO_Pin - 32);
374 switch (GPIO_PinConfig)
375 {
376 case GPIO_PinOutput:
377 GPIOB->PDDR |= (1<<GPIO_Pin); /* Enable Port Data Direction Register */
378 GPIOB->PIDR |= (1<<GPIO_Pin); /* Set Port Input Disable Register */
379 PORT->PUEH &= ~(1<<GPIO_Pin); /* Disable Pullup */
380 break;
381 case GPIO_PinInput:
382 GPIOB->PDDR &= ~(1<<GPIO_Pin); /* Disable Port Data Direction Register */
383 GPIOB->PIDR &= ~(1<<GPIO_Pin); /* Clear Port Input Disable Register */
384 PORT->PUEH &= ~(1<<GPIO_Pin); /* Disable Pullup */
385 break;
386 case GPIO_PinInput_InternalPullup:
387 GPIOB->PDDR &= ~(1<<GPIO_Pin); /* Disable Port Data Direction Register */
388 GPIOB->PIDR &= ~(1<<GPIO_Pin); /* Clear Port Input Disable Register */
389 PORT->PUEH |= (1<<GPIO_Pin); /* Enable Pullup */
390 break;
391 case GPIO_PinOutput_HighCurrent:
392 GPIOB->PDDR |= (1<<GPIO_Pin); /* Enable Port Data Direction Register */
393 GPIOB->PIDR |= (1<<GPIO_Pin); /* Set Port Input Disable Register */
394 PORT->PUEH &= ~(1<<GPIO_Pin); /* Disable Pullup */
395 break;
396 }
397 }
398 #endif
399
400 #if defined(CPU_NV32M3)
401 if (GPIO_Pin < GPIO_PTE0)
402 {
403 switch (GPIO_PinConfig)
404 {
405 case GPIO_PinOutput:
406 GPIOA->PDDR |= (1<<GPIO_Pin); /* Enable Port Data Direction Register */
407 GPIOA->PIDR |= (1<<GPIO_Pin); /* Set Port Input Disable Register */
408 PORT->PUEL &= ~(1<<GPIO_Pin); /* Disable Pullup */
409 break;
410 case GPIO_PinInput:
411 GPIOA->PDDR &= ~(1<<GPIO_Pin); /* Disable Port Data Direction Register */
412 GPIOA->PIDR &= ~(1<<GPIO_Pin); /* Clear Port Input Disable Register */
413 PORT->PUEL &= ~(1<<GPIO_Pin); /* Disable Pullup */
414 break;
415 case GPIO_PinInput_InternalPullup:
416 GPIOA->PDDR &= ~(1<<GPIO_Pin); /* Disable Port Data Direction Register */
417 GPIOA->PIDR &= ~(1<<GPIO_Pin); /* Clear Port Input Disable Register */
418 PORT->PUEL |= (1<<GPIO_Pin); /* Enable Pullup */
419 break;
420 case GPIO_PinOutput_HighCurrent:
421 GPIOA->PDDR |= (1<<GPIO_Pin); /* Enable Port Data Direction Register */
422 GPIOA->PIDR |= (1<<GPIO_Pin); /* Set Port Input Disable Register */
423 PORT->PUEL &= ~(1<<GPIO_Pin); /* Disable Pullup */
424 break;
425 }
426 }
427 #endif
428
429
430 #if defined(CPU_NV32M4)
431 if (GPIO_Pin < GPIO_PTE0)
432 {
433 switch (GPIO_PinConfig)
434 {
435 case GPIO_PinOutput:
436 GPIOA->PDDR |= (1<<GPIO_Pin); /* Enable Port Data Direction Register */
437 GPIOA->PIDR |= (1<<GPIO_Pin); /* Set Port Input Disable Register */
438 PORT->PUE0 &= ~(1<<GPIO_Pin); /* Disable Pullup */
439 break;
440 case GPIO_PinInput:
441 GPIOA->PDDR &= ~(1<<GPIO_Pin); /* Disable Port Data Direction Register */
442 GPIOA->PIDR &= ~(1<<GPIO_Pin); /* Clear Port Input Disable Register */
443 PORT->PUE0 &= ~(1<<GPIO_Pin); /* Disable Pullup */
444 break;
445 case GPIO_PinInput_InternalPullup:
446 GPIOA->PDDR &= ~(1<<GPIO_Pin); /* Disable Port Data Direction Register */
447 GPIOA->PIDR &= ~(1<<GPIO_Pin); /* Clear Port Input Disable Register */
448 PORT->PUE0 |= (1<<GPIO_Pin); /* Enable Pullup */
449 break;
450 case GPIO_PinOutput_HighCurrent:
451 GPIOA->PDDR |= (1<<GPIO_Pin); /* Enable Port Data Direction Register */
452 GPIOA->PIDR |= (1<<GPIO_Pin); /* Set Port Input Disable Register */
453 PORT->PUE0 &= ~(1<<GPIO_Pin); /* Disable Pullup */
454 break;
455 }
456 }
457 else if (GPIO_Pin < GPIO_PTI0)
458 {
459 GPIO_Pin = (GPIO_PinType)(GPIO_Pin - 32);
460 switch (GPIO_PinConfig)
461 {
462 case GPIO_PinOutput:
463 GPIOB->PDDR |= (1<<GPIO_Pin); /* Enable Port Data Direction Register */
464 GPIOB->PIDR |= (1<<GPIO_Pin); /* Set Port Input Disable Register */
465 PORT->PUE1 &= ~(1<<GPIO_Pin); /* Disable Pullup */
466 break;
467 case GPIO_PinInput:
468 GPIOB->PDDR &= ~(1<<GPIO_Pin); /* Disable Port Data Direction Register */
469 GPIOB->PIDR &= ~(1<<GPIO_Pin); /* Clear Port Input Disable Register */
470 PORT->PUE1 &= ~(1<<GPIO_Pin); /* Disable Pullup */
471 break;
472 case GPIO_PinInput_InternalPullup:
473 GPIOB->PDDR &= ~(1<<GPIO_Pin); /* Disable Port Data Direction Register */
474 GPIOB->PIDR &= ~(1<<GPIO_Pin); /* Clear Port Input Disable Register */
475 PORT->PUE1 |= (1<<GPIO_Pin); /* Enable Pullup */
476 break;
477 case GPIO_PinOutput_HighCurrent:
478 GPIOB->PDDR |= (1<<GPIO_Pin); /* Enable Port Data Direction Register */
479 GPIOB->PIDR |= (1<<GPIO_Pin); /* Set Port Input Disable Register */
480 PORT->PUE1 &= ~(1<<GPIO_Pin); /* Disable Pullup */
481 break;
482 }
483 }
484 else
485 {
486 GPIO_Pin = (GPIO_PinType)(GPIO_Pin - 64);
487 switch (GPIO_PinConfig)
488 {
489 case GPIO_PinOutput:
490 GPIOC->PDDR |= (1<<GPIO_Pin); /* Enable Port Data Direction Register */
491 GPIOC->PIDR |= (1<<GPIO_Pin); /* Set Port Input Disable Register */
492 PORT->PUE2 &= ~(1<<GPIO_Pin); /* Disable Pullup */
493 break;
494 case GPIO_PinInput:
495 GPIOC->PDDR &= ~(1<<GPIO_Pin); /* Disable Port Data Direction Register */
496 GPIOC->PIDR &= ~(1<<GPIO_Pin); /* Clear Port Input Disable Register */
497 PORT->PUE2 &= ~(1<<GPIO_Pin); /* Disable Pullup */
498 break;
499 case GPIO_PinInput_InternalPullup:
500 GPIOC->PDDR &= ~(1<<GPIO_Pin); /* Disable Port Data Direction Register */
501 GPIOC->PIDR &= ~(1<<GPIO_Pin); /* Clear Port Input Disable Register */
502 PORT->PUE2 |= (1<<GPIO_Pin); /* Enable Pullup */
503 break;
504 case GPIO_PinOutput_HighCurrent:
505 GPIOC->PDDR |= (1<<GPIO_Pin); /* Enable Port Data Direction Register */
506 GPIOC->PIDR |= (1<<GPIO_Pin); /* Set Port Input Disable Register */
507 PORT->PUE2 &= ~(1<<GPIO_Pin); /* Disable Pullup */
508 break;
509 }
510 }
511 #endif
512
513 /* Config GPIO HDRV */
514 if(GPIO_PinConfig == GPIO_PinOutput_HighCurrent)
515 {
516 #if defined(CPU_NV32M3)
517 switch (GPIO_Pin)
518 {
519 case GPIO_PTB5:
520 PORT->HDRVE |= PORT_HDRVE_PTB5_MASK;
521 break;
522 case GPIO_PTC1:
523 PORT->HDRVE |= PORT_HDRVE_PTC1_MASK;
524 break;
525 case GPIO_PTC5:
526 PORT->HDRVE |= PORT_HDRVE_PTC5_MASK;
527 break;
528 default:
529 break;
530 }
531 #endif
532
533 #if defined(CPU_NV32M4) | defined(CPU_NV32)
534 switch (GPIO_Pin)
535 {
536 case GPIO_PTB4:
537 PORT->HDRVE |= PORT_HDRVE_PTB4_MASK;
538 break;
539 case GPIO_PTB5:
540 PORT->HDRVE |= PORT_HDRVE_PTB5_MASK;
541 break;
542 case GPIO_PTD0:
543 PORT->HDRVE |= PORT_HDRVE_PTD0_MASK;
544 break;
545 case GPIO_PTD1:
546 PORT->HDRVE |= PORT_HDRVE_PTD1_MASK;
547 break;
548 case GPIO_PTE0:
549 PORT->HDRVE |= PORT_HDRVE_PTE0_MASK;
550 break;
551 case GPIO_PTE1:
552 PORT->HDRVE |= PORT_HDRVE_PTE1_MASK;
553 break;
554 case GPIO_PTH0:
555 PORT->HDRVE |= PORT_HDRVE_PTH0_MASK;
556 break;
557 case GPIO_PTH1:
558 PORT->HDRVE |= PORT_HDRVE_PTH1_MASK;
559 break;
560 default:
561 break;
562 }
563 #endif
564 }
565 }
566
567 /*****************************************************************************//*!
568 * @brief Toggle GPIO single pin which is specified by GPIO_Pin
569 *
570 * @param[in] GPIO_Pin GPIO pin name, can be GPIO_PTA0,1 ...
571 *
572 * @return none
573 *
574 * @ Pass/ Fail criteria: none
575 *****************************************************************************/
GPIO_PinToggle(GPIO_PinType GPIO_Pin)576 void GPIO_PinToggle(GPIO_PinType GPIO_Pin)
577 {
578 /* Sanity check */
579 ASSERT(GPIO_Pin <= GPIO_PTI7);
580
581 if (GPIO_Pin < GPIO_PTE0)
582 {
583 /* PTA0-7, PTB0-7, PTC0-7, PTD0-7 */
584 GPIOA->PTOR = (1<<GPIO_Pin);
585 }
586
587 #if (defined(CPU_NV32) | defined(CPU_NV32M4))
588
589 else if (GPIO_Pin < GPIO_PTI0)
590 {
591 /* PTE0-7, PTF0-7, PTH0-7, PTI0-7 */
592 GPIO_Pin = (GPIO_PinType)(GPIO_Pin - GPIO_PTE0);
593 GPIOB->PTOR = (1<<GPIO_Pin);
594 }
595 #endif
596
597 #if defined(CPU_NV32M4)
598 else if(GPIO_Pin < GPIO_PIN_MAX)
599 {
600 /* PTI0-7 */
601 GPIO_Pin = (GPIO_PinType)(GPIO_Pin - GPIO_PTI0);
602 GPIOC->PTOR = (1<<GPIO_Pin);
603 }
604 #endif
605 }
606
607 /*****************************************************************************//*!
608 * @brief Set GPIO single pin which is specified by GPIO_Pin
609 *
610 * @param[in] GPIO_Pin GPIO pin name, can be GPIO_PTA0,1 ...
611 *
612 * @return none
613 *
614 * @ Pass/ Fail criteria: none
615 *****************************************************************************/
GPIO_PinSet(GPIO_PinType GPIO_Pin)616 void GPIO_PinSet(GPIO_PinType GPIO_Pin)
617 {
618 /* Sanity check */
619 ASSERT(GPIO_Pin <= GPIO_PTI7);
620
621 if (GPIO_Pin < GPIO_PTE0)
622 {
623 /* PTA0-7, PTB0-7, PTC0-7, PTD0-7 */
624 GPIOA->PSOR = (1<<GPIO_Pin);
625 }
626
627 #if (defined(CPU_NV32) | defined(CPU_NV32M4))
628
629 else if (GPIO_Pin < GPIO_PTI0)
630 {
631 /* PTE0-7, PTF0-7, PTH0-7, PTI0-7 */
632 GPIO_Pin = (GPIO_PinType)(GPIO_Pin - GPIO_PTE0);
633 GPIOB->PSOR = (1<<GPIO_Pin);
634 }
635 #endif
636
637 #if defined(CPU_NV32M4)
638 else if(GPIO_Pin < GPIO_PIN_MAX)
639 {
640 /* PTI0-7 */
641 GPIO_Pin = (GPIO_PinType)(GPIO_Pin - GPIO_PTI0);
642 GPIOC->PSOR = (1<<GPIO_Pin);
643 }
644 #endif
645 }
646
647 /*****************************************************************************//*!
648 * @brief Clear GPIO single pin which is specified by GPIO_Pin
649 *
650 * @param[in] GPIO_Pin GPIO pin name, can be GPIO_PTA0,1 ...
651 *
652 * @return none
653 *
654 * @ Pass/ Fail criteria: none
655 *****************************************************************************/
GPIO_PinClear(GPIO_PinType GPIO_Pin)656 void GPIO_PinClear(GPIO_PinType GPIO_Pin)
657 {
658 /* Sanity check */
659 ASSERT(GPIO_Pin <= GPIO_PTI7);
660
661 if (GPIO_Pin < GPIO_PTE0)
662 {
663 /* PTA0-7, PTB0-7, PTC0-7, PTD0-7 */
664 GPIOA->PCOR = (1<<GPIO_Pin);
665 }
666
667 #if (defined(CPU_NV32) | defined(CPU_NV32M4))
668
669 else if (GPIO_Pin < GPIO_PTI0)
670 {
671 /* PTE0-7, PTF0-7, PTH0-7, PTI0-7 */
672 GPIO_Pin = (GPIO_PinType)(GPIO_Pin - GPIO_PTE0);
673 GPIOB->PCOR = (1<<GPIO_Pin);
674 }
675 #endif
676
677 #if defined(CPU_NV32M4)
678 else if(GPIO_Pin < GPIO_PIN_MAX)
679 {
680 /* PTI0-7 */
681 GPIO_Pin = (GPIO_PinType)(GPIO_Pin - GPIO_PTI0);
682 GPIOC->PCOR = (1<<GPIO_Pin);
683 }
684 #endif
685 }
686
687 /*! @} End of gpio_api_list */
688
689