1
2 /******************************************************************************
3 *
4 * @brief providing APIs for system integration module (SIM).
5 *
6 *******************************************************************************
7 *
8 * provide APIs for SIM
9 ******************************************************************************/
10 #include "common.h"
11 #include "sim.h"
12
13 /******************************************************************************
14 * Global variables
15 ******************************************************************************/
16
17 /******************************************************************************
18 * Constants and macros
19 ******************************************************************************/
20
21 /******************************************************************************
22 * Local types
23 ******************************************************************************/
24
25 /******************************************************************************
26 * Local function prototypes
27 ******************************************************************************/
28
29 /******************************************************************************
30 * Local variables
31 ******************************************************************************/
32
33 /******************************************************************************
34 * Local functions
35 ******************************************************************************/
36
37 /******************************************************************************
38 * Global functions
39 ******************************************************************************/
40
41 /******************************************************************************
42 * define SIM API list
43 *
44 *//*! @addtogroup sim_api_list
45 * @{
46 *******************************************************************************/
47 #if defined(CPU_NV32)
48 /*****************************************************************************//*!
49 *
50 * @brief initialize SIM registers.
51 *
52 * @param[in] pConfig pointer to SIM configuration.
53 *
54 * @return none
55 *
56 * @ Pass/ Fail criteria: none
57 * @see SIM_ConfigType
58 *****************************************************************************/
SIM_Init(SIM_ConfigType * pConfig)59 void SIM_Init(SIM_ConfigType *pConfig)
60 {
61 uint32_t u32Sopt;
62 uint32_t u32PinSel;
63 uint32_t u32Scgc;
64 uint32_t u32BusDiv;
65 /*
66 * intialize the registers to reset default values
67 */
68 u32Sopt = 0x0010000E; /* enable SWD, RESET, and NMI pins */
69 u32PinSel = 0;
70 u32Scgc = 0x00003000; /* enable SWD and FLASH */
71 u32BusDiv = 0;
72 u32BusDiv = pConfig->sBits.bBusDiv;
73 if(pConfig->sBits.bDisableNMI)
74 {
75 u32Sopt &= ~SIM_SOPT_NMIE_MASK;
76 }
77 if(pConfig->sBits.bDisableRESET)
78 {
79 u32Sopt &= ~SIM_SOPT_RSTPE_MASK;
80 }
81 if(pConfig->sBits.bDisableSWD)
82 {
83 u32Sopt &= ~SIM_SOPT_SWDE_MASK;
84 }
85 if(pConfig->sBits.bEnableCLKOUT)
86 {
87 u32Sopt |= SIM_SOPT_CLKOE_MASK;
88 }
89 if(pConfig->sBits.bETMSYNC)
90 {
91 u32Sopt |= SIM_SOPT_ETMSYNC_MASK;
92 }
93 if(pConfig->sBits.bRXDCE)
94 {
95 u32Sopt |= SIM_SOPT_RXDCE_MASK;
96 }
97 if(pConfig->sBits.bTXDME)
98 {
99 u32Sopt |= SIM_SOPT_TXDME_MASK;
100 }
101 if(pConfig->sBits.bACIC)
102 {
103 u32Sopt |= SIM_SOPT_ACIC_MASK;
104 }
105 if(pConfig->sBits.bRTCC)
106 {
107 u32Sopt |= SIM_SOPT_RTCC_MASK;
108 }
109 if(pConfig->sBits.bRXDFE)
110 {
111 u32Sopt |= SIM_SOPT_RXDFE_MASK;
112 }
113 u32Sopt |= ((pConfig->u8BusRef & 0x07) << 16);
114 u32Sopt |= ((pConfig->u8Delay) << 24);
115 u32Sopt |= ((pConfig->sBits.u8ADHWT & 0x03) << 8);
116 u32PinSel = pConfig->u32PinSel;
117 u32Scgc = pConfig->u32SCGC;
118
119 /* write SIM registers */
120 SIM->SOPT = u32Sopt;
121 SIM->PINSEL = u32PinSel;
122 SIM->SCGC = u32Scgc;
123 SIM->BUSDIV = u32BusDiv;
124 }
125 #elif defined(CPU_NV32M3)
126 /*****************************************************************************//*!
127 *
128 * @brief initialize SIM registers.
129 *
130 * @param[in] pConfig pointer to SIM configuration.
131 *
132 * @return none
133 *
134 * @ Pass/ Fail criteria: none
135 * @see SIM_ConfigType
136 *****************************************************************************/
137
SIM_Init(SIM_ConfigType * pConfig)138 void SIM_Init(SIM_ConfigType *pConfig)
139 {
140 uint32_t u32Sopt;
141 uint32_t u32PinSel;
142 uint32_t u32Scgc;
143 uint32_t u32ClockDiv;
144 /*
145 * intialize the registers to reset default values
146 */
147 u32Sopt = 0x0010000E; /* enable SWD, RESET, and NMI pins */
148 u32PinSel = 0;
149 u32Scgc = 0x00003000; /* enable SWD and FLASH */
150 u32ClockDiv = 0;
151 u32ClockDiv = pConfig->u32CLKDIV;
152 if(pConfig->sBits.bDisableNMI)
153 {
154 u32Sopt &= ~SIM_SOPT_NMIE_MASK;
155 }
156 if(pConfig->sBits.bDisableRESET)
157 {
158 u32Sopt &= ~SIM_SOPT_RSTPE_MASK;
159 }
160 if(pConfig->sBits.bDisableSWD)
161 {
162 u32Sopt &= ~SIM_SOPT_SWDE_MASK;
163 }
164 if(pConfig->sBits.bEnableCLKOUT)
165 {
166 u32Sopt |= SIM_SOPT_CLKOE_MASK;
167 }
168 if(pConfig->sBits.bETMSYNC)
169 {
170 u32Sopt |= SIM_SOPT_ETMSYNC_MASK;
171 }
172 if(pConfig->sBits.bRXDCE)
173 {
174 u32Sopt |= SIM_SOPT_RXDCE_MASK;
175 }
176 if(pConfig->sBits.bTXDME)
177 {
178 u32Sopt |= SIM_SOPT_TXDME_MASK;
179 }
180 if(pConfig->sBits.bACTRG)
181 {
182 u32Sopt |= SIM_SOPT_ACTRG_MASK;
183 }
184 u32Sopt |= ((pConfig->u8BusRef & 0x07) << 16);
185 u32Sopt |= ((pConfig->u8Delay) << 24);
186 u32Sopt |= ((pConfig->sBits.u8ADHWT & 0x07) << 20);
187 u32Sopt |= ((pConfig->sBits.bRXDFE)&0x03<<8);
188 u32Sopt |= ((pConfig->sBits.bETMIC)&0x03<<6);
189
190 u32PinSel = pConfig->u32PinSel;
191 u32Scgc = pConfig->u32SCGC;
192 /* write SIM registers */
193 SIM->SOPT = u32Sopt;
194 SIM->PINSEL = u32PinSel;
195 SIM->SCGC = u32Scgc;
196 SIM->CLKDIV = u32ClockDiv;
197 }
198 #elif defined(CPU_NV32M4)
199 /*****************************************************************************//*!
200 *
201 * @brief initialize SIM registers.
202 *
203 * @param[in] pConfig pointer to SIM configuration.
204 *
205 * @return none
206 *
207 * @ Pass/ Fail criteria: none
208 * @see SIM_ConfigType
209 *****************************************************************************/
SIM_Init(SIM_ConfigType * pConfig)210 void SIM_Init(SIM_ConfigType *pConfig)
211 {
212 uint32_t u32Sopt;
213 uint32_t u32PinSel;
214 uint32_t u32Scgc;
215 uint32_t u32ClockDiv;
216 /*
217 * intialize the registers to reset default values
218 */
219 u32Sopt = 0x0E; /* enable SWD, RESET, and NMI pins */
220 u32PinSel = 0;
221 u32Scgc = 0x00003000; /* enable SWD and FLASH */
222 u32ClockDiv = 0;
223 u32ClockDiv = pConfig->u32CLKDIV;
224 if(pConfig->sBits.bDisableNMI)
225 {
226 u32Sopt &= ~SIM_SOPT0_NMIE_MASK;
227 }
228 if(pConfig->sBits.bDisableRESET)
229 {
230 u32Sopt &= ~SIM_SOPT0_RSTPE_MASK;
231 }
232 if(pConfig->sBits.bDisableSWD)
233 {
234 u32Sopt &= ~SIM_SOPT0_SWDE_MASK;
235 }
236 if(pConfig->sBits.bEnableCLKOUT)
237 {
238 u32Sopt |= SIM_SOPT0_CLKOE_MASK;
239 }
240 if(pConfig->sBits.bETMSYNC)
241 {
242 u32Sopt |= SIM_SOPT0_ETMSYNC_MASK;
243 }
244 if(pConfig->sBits.bRXDCE)
245 {
246 u32Sopt |= SIM_SOPT0_RXDCE_MASK;
247 }
248 if(pConfig->sBits.bTXDME)
249 {
250 u32Sopt |= SIM_SOPT0_TXDME_MASK;
251 }
252 if(pConfig->sBits.bACTRG)
253 {
254 u32Sopt |= SIM_SOPT0_ACTRG_MASK;
255 }
256 u32Sopt |= ((pConfig->u8BusRef & 0x07) << 16);
257 u32Sopt |= ((pConfig->u8Delay) << 24);
258 u32Sopt |= ((pConfig->sBits.u8ADHWT & 0x07) << 20);
259 u32Sopt |= ((pConfig->sBits.bRXDFE)&0x03<<8);
260 //u32Sopt |= ((pConfig->sBits.bETMIC)&0x03<<6);
261
262 u32PinSel = pConfig->u32PinSel;
263 u32Scgc = pConfig->u32SCGC;
264 /* write SIM registers */
265 SIM->SOPT0 = u32Sopt;
266 SIM->PINSEL = u32PinSel;
267 SIM->SCGC = u32Scgc;
268 SIM->CLKDIV = u32ClockDiv;
269 }
270 #endif
271
272 /*****************************************************************************//*!
273 *
274 * @brief set SIM clock gating registers to enable or disable peripheral clocks.
275 *
276 * @param[in] u32PeripheralMask peripherial bits mask.
277 * @param[in] u8GateOn 1: ON, 0: OFF.
278 *
279 * @return none
280 *
281 * @ Pass/ Fail criteria: none
282 *****************************************************************************/
283
SIM_SetClockGating(uint32_t u32PeripheralMask,uint8_t u8GateOn)284 void SIM_SetClockGating(uint32_t u32PeripheralMask, uint8_t u8GateOn)
285 {
286 uint32_t u32Scgc;
287
288 /*
289 * save original clock gating value
290 */
291 u32Scgc = SIM->SCGC;
292
293 if(u8GateOn)
294 {
295 u32Scgc |= u32PeripheralMask;
296 }
297 else
298 {
299 u32Scgc &= ~u32PeripheralMask;
300 }
301
302 SIM->SCGC = u32Scgc;
303 }
304
305
306 /*****************************************************************************//*!
307 *
308 * @brief read the corresponding status flags.
309 *
310 * @param[in] u32StatusMask indicates which status to be read.
311 *
312 * @return status.
313 *
314 * @ Pass/ Fail criteria: none
315 *****************************************************************************/
SIM_GetStatus(uint32_t u32StatusMask)316 uint32_t SIM_GetStatus(uint32_t u32StatusMask)
317 {
318 uint32_t u32Status;
319
320 u32Status = SIM->SRSID & u32StatusMask;
321 return (u32Status);
322 }
323
324 /*****************************************************************************//*!
325 *
326 * @brief read the corresponding ID.
327 *
328 * @param[in] u8ID type of ID.
329 *
330 * @return ID
331 *
332 * @ Pass/ Fail criteria: none.
333 * @see IDType.
334 *****************************************************************************/
SIM_ReadID(IDType sID)335 uint8_t SIM_ReadID(IDType sID)
336 {
337 uint32_t u32ID;
338 uint8_t u8IDOffset[4] =
339 {
340 28, 24, 20,16
341 };
342 u32ID = (SIM->SRSID >> u8IDOffset[sID]) & 0x0F;
343 return (u32ID);
344 }
345 /*! @} End of sim_api_list */
346
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