1;/*****************************************************************************
2; * @file:    startup_NV32.s
3; * @purpose: CMSIS Cortex-M0plus Core Device Startup File for the
4; *           NV32F100
5;*
6; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
7; *
8; *****************************************************************************/
9
10
11; <h> Stack Configuration
12;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
13; </h>
14
15Stack_Size      EQU     0x00000200
16
17                AREA    STACK, NOINIT, READWRITE, ALIGN=3
18Stack_Mem       SPACE   Stack_Size
19__initial_sp
20
21
22; <h> Heap Configuration
23;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
24; </h>
25
26Heap_Size       EQU     0x00000200
27
28                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
29__heap_base
30Heap_Mem        SPACE   Heap_Size
31__heap_limit
32
33
34                PRESERVE8
35                THUMB
36
37; Vector Table Mapped to Address 0 at Reset
38
39                AREA    RESET, DATA, READONLY
40                EXPORT  __Vectors
41                EXPORT  __Vectors_End
42                EXPORT  __Vectors_Size
43
44__Vectors       DCD     __initial_sp  ; Top of Stack
45                DCD     Reset_Handler  ; Reset Handler
46                DCD     NMI_Handler  ; NMI Handler
47                DCD     0  ; Reserved
48                DCD     0  ; Reserved
49                DCD     0  ; Reserved
50                DCD     0  ; Reserved
51                DCD     0  ; Reserved
52                DCD     0  ; Reserved
53                DCD     0  ; Reserved
54                DCD     0  ; Reserved
55                DCD     SVC_Handler  ; SVCall Handler
56                DCD     0  ; Reserved
57                DCD     0  ; Reserved
58                DCD     PendSV_Handler  ; PendSV Handler
59                DCD     SysTick_Handler  ; SysTick Handler
60
61                ; External Interrupts
62                DCD     Reserved16_IRQHandler  ; Reserved interrupt 16
63                DCD     Reserved17_IRQHandler  ; Reserved interrupt 17
64                DCD     Reserved18_IRQHandler  ; Reserved interrupt 18
65                DCD     Reserved19_IRQHandler  ; Reserved interrupt 19
66                DCD     Reserved20_IRQHandler  ; Reserved interrupt 20
67                DCD     ETMRH_IRQHandler  ; ETMRH command complete/read collision interrupt
68                DCD     LVD_LVW_IRQHandler  ; Low Voltage Detect, Low Voltage Warning
69                DCD     IRQ_IRQHandler  ; External interrupt
70                DCD     I2C0_IRQHandler  ; I2C0 interrupt
71                DCD     Reserved25_IRQHandler  ; Reserved interrupt 25
72                DCD     SPI0_IRQHandler  ; SPI0 interrupt
73                DCD     SPI1_IRQHandler  ; SPI1 interrupt
74                DCD     UART0_IRQHandler  ; UART0 status/error interrupt
75                DCD     UART1_IRQHandler  ; UART1 status/error interrupt
76                DCD     UART2_IRQHandler  ; UART2 status/error interrupt
77                DCD     ADC0_IRQHandler  ; ADC0 interrupt
78                DCD     ACMP0_IRQHandler  ; ACMP0 interrupt
79                DCD     ETM0_IRQHandler  ; ETM0 Single interrupt vector for all sources
80                DCD     ETM1_IRQHandler  ; ETM1 Single interrupt vector for all sources
81                DCD     ETM2_IRQHandler  ; ETM2 Single interrupt vector for all sources
82                DCD     RTC_IRQHandler  ; RTC overflow
83                DCD     ACMP1_IRQHandler  ; ACMP1 interrupt
84                DCD     PIT_CH0_IRQHandler  ; PIT CH0 overflow
85                DCD     PIT_CH1_IRQHandler  ; PIT CH1 overflow
86                DCD     KBI0_IRQHandler  ; Keyboard interrupt 0
87                DCD     KBI1_IRQHandler  ; Keyboard interrupt 1
88                DCD     Reserved42_IRQHandler  ; Reserved interrupt 42
89                DCD     ICS_IRQHandler  ; MCG interrupt
90                DCD     Watchdog_IRQHandler  ; WDOG Interrupt
91                DCD     Reserved45_IRQHandler  ; Reserved interrupt 45
92                DCD     Reserved46_IRQHandler  ; Reserved interrupt 46
93                DCD     Reserved47_IRQHandler  ; Reserved interrupt 47
94__Vectors_End
95
96__Vectors_Size 	EQU     __Vectors_End - __Vectors
97
98; <h> Flash Configuration
99;   <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
100;   <i> and security information that allows the MCU to restrict acces to the FTFL module.
101;   <h> Backdoor Comparison Key
102;     <o0>  Backdoor Key 0  <0x0-0xFF:2>
103;     <o1>  Backdoor Key 1  <0x0-0xFF:2>
104;     <o2>  Backdoor Key 2  <0x0-0xFF:2>
105;     <o3>  Backdoor Key 3  <0x0-0xFF:2>
106;     <o4>  Backdoor Key 4  <0x0-0xFF:2>
107;     <o5>  Backdoor Key 5  <0x0-0xFF:2>
108;     <o6>  Backdoor Key 6  <0x0-0xFF:2>
109;     <o7>  Backdoor Key 7  <0x0-0xFF:2>
110BackDoorK0      EQU     0xFF
111BackDoorK1      EQU     0xFF
112BackDoorK2      EQU     0xFF
113BackDoorK3      EQU     0xFF
114BackDoorK4      EQU     0xFF
115BackDoorK5      EQU     0xFF
116BackDoorK6      EQU     0xFF
117BackDoorK7      EQU     0xFF
118;   </h>
119;   <h> EEPROM Protection Register (EEPROT)
120;     <i> The DFPROT register defines which D-Flash sectors are protected against program and erase operations.
121;     <o.7>  DPOPEN
122;       <0=> Enables EEPROM memory protection
123;       <1=> Disables EEPROM memory protection
124;     <o.0..2> DPS
125;       <0=> Flash address range: 0x00_0000 - 0x00_001F; protected size: 32 bytes
126;       <1=> Flash address range: 0x00_0000 - 0x00_003F; protected size: 64 bytes
127;       <2=> Flash address range: 0x00_0000 - 0x00_005F; protected size: 96 bytes
128;       <3=> Flash address range: 0x00_0000 - 0x00_007F; protected size: 128 bytes
129;       <4=> Flash address range: 0x00_0000 - 0x00_009F; protected size: 160 bytes
130;       <5=> Flash address range: 0x00_0000 - 0x00_00BF; protected size: 192 bytes
131;       <6=> Flash address range: 0x00_0000 - 0x00_00DF; protected size: 224 bytes
132;       <7=> Flash address range: 0x00_0000 - 0x00_00FF; protected size: 256 bytes
133EEPROT          EQU     0xFF
134;     </h>
135;     <h> FPROT
136;       <i> P-Flash Protection Register
137;       <o.7> FPOPEN
138;         <0=> FPHDIS and FPLDIS bits define unprotected address ranges as specified by the corresponding FPHS and FPLS bits FPROT1.1
139;         <1=> FPHDIS and FPLDIS bits enable protection for the address range specified by the corresponding FPHS and FPLS bits
140;       <o.5> FPHDIS
141;         <0=> Protection/Unprotection enabled
142;         <1=> Protection/Unprotection disabled
143;       <o.3..4> FPHS
144;         <0=> Address range: 0x00_7C00-0x00_7FFF; protected size: 1 KB
145;         <1=> Address range: 0x00_7800-0x00_7FFF; protected size: 2 KB
146;         <2=> Address range: 0x00_7000-0x00_7FFF; protected size: 4 KB
147;         <3=> Address range: 0x00_6000-0x00_7FFF; protected size: 8 KB
148;       <o.5> FPLDIS
149;         <0=> Protection/Unprotection enabled
150;         <1=> Protection/Unprotection disabled
151;       <o.3..4> FPLS
152;         <0=> Address range: 0x00_0000-0x00_07FF; protected size: 2 KB
153;         <1=> Address range: 0x00_0000-0x00_0FFF; protected size: 4 KB
154;         <2=> Address range: 0x00_0000-0x00_1FFF; protected size: 8 KB
155;         <3=> Address range: 0x00_0000-0x00_3FFF; protected size: 16 KB
156FPROT         EQU     0xFF
157;     </h>
158;   </h>
159;   <h> Flash security byte (FSEC)
160;     <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
161;     <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
162;     <o.0..1> SEC
163;       <2=> MCU security status is unsecure
164;       <3=> MCU security status is secure
165;         <i> Flash Security
166;         <i> This bits define the security state of the MCU.
167;     <o.6..7> KEYEN
168;       <2=> Backdoor key access enabled
169;       <3=> Backdoor key access disabled
170;         <i> Backdoor key Security Enable
171;         <i> These bits enable and disable backdoor key access to the FTFL module.
172FSEC            EQU     0xFE
173;   </h>
174;   <h> Flash Option Register (FOPT)
175FOPT            EQU     0xFE
176;   </h>
177                IF      :LNOT::DEF:RAM_TARGET
178                AREA    |.ARM.__at_0x400|, CODE, READONLY
179                DCB     BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
180                DCB     BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
181                DCB     0xFF,       0xFF,       0xFF,       0xFF
182                DCB     EEPROT,      FPROT,     FSEC,       FOPT              ;Modified by ARM.  DCB     FPROT,      EEPROT,     FOPT,       FSEC
183                ENDIF
184
185                AREA    |.text|, CODE, READONLY
186
187
188; Reset Handler
189
190Reset_Handler   PROC
191                EXPORT  Reset_Handler             [WEAK]
192                IMPORT  SystemInit
193                IMPORT  __main
194                LDR     R0, =SystemInit
195                BLX     R0
196                LDR     R0, =__main
197                BX      R0
198                ENDP
199
200
201; Dummy Exception Handlers (infinite loops which can be modified)
202
203NMI_Handler     PROC
204                EXPORT  NMI_Handler               [WEAK]
205                B       .
206                ENDP
207HardFault_Handler\
208                PROC
209                EXPORT  HardFault_Handler         [WEAK]
210                B       .
211                ENDP
212MemManage_Handler\
213                PROC
214                EXPORT  MemManage_Handler         [WEAK]
215                B       .
216                ENDP
217BusFault_Handler\
218                PROC
219                EXPORT  BusFault_Handler          [WEAK]
220                B       .
221                ENDP
222UsageFault_Handler\
223                PROC
224                EXPORT  UsageFault_Handler        [WEAK]
225                B       .
226                ENDP
227SVC_Handler     PROC
228                EXPORT  SVC_Handler               [WEAK]
229                B       .
230                ENDP
231DebugMon_Handler\
232                PROC
233                EXPORT  DebugMon_Handler          [WEAK]
234                B       .
235                ENDP
236PendSV_Handler  PROC
237                EXPORT  PendSV_Handler            [WEAK]
238                B       .
239                ENDP
240SysTick_Handler PROC
241                EXPORT  SysTick_Handler           [WEAK]
242                B       .
243                ENDP
244
245Default_Handler PROC
246                EXPORT  Reserved16_IRQHandler     [WEAK]
247                EXPORT  Reserved17_IRQHandler     [WEAK]
248                EXPORT  Reserved18_IRQHandler     [WEAK]
249                EXPORT  Reserved19_IRQHandler     [WEAK]
250                EXPORT  Reserved20_IRQHandler     [WEAK]
251                EXPORT  ETMRH_IRQHandler     [WEAK]
252                EXPORT  LVD_LVW_IRQHandler     [WEAK]
253                EXPORT  IRQ_IRQHandler     [WEAK]
254                EXPORT  I2C0_IRQHandler     [WEAK]
255                EXPORT  Reserved25_IRQHandler     [WEAK]
256                EXPORT  SPI0_IRQHandler     [WEAK]
257                EXPORT  SPI1_IRQHandler     [WEAK]
258                EXPORT  UART0_IRQHandler     [WEAK]
259                EXPORT  UART1_IRQHandler     [WEAK]
260                EXPORT  UART2_IRQHandler     [WEAK]
261                EXPORT  ADC0_IRQHandler     [WEAK]
262                EXPORT  ACMP0_IRQHandler     [WEAK]
263                EXPORT  ETM0_IRQHandler     [WEAK]
264                EXPORT  ETM1_IRQHandler     [WEAK]
265                EXPORT  ETM2_IRQHandler     [WEAK]
266                EXPORT  RTC_IRQHandler     [WEAK]
267                EXPORT  ACMP1_IRQHandler     [WEAK]
268                EXPORT  PIT_CH0_IRQHandler     [WEAK]
269                EXPORT  PIT_CH1_IRQHandler     [WEAK]
270                EXPORT  KBI0_IRQHandler     [WEAK]
271                EXPORT  KBI1_IRQHandler     [WEAK]
272                EXPORT  Reserved42_IRQHandler     [WEAK]
273                EXPORT  ICS_IRQHandler     [WEAK]
274                EXPORT  Watchdog_IRQHandler     [WEAK]
275                EXPORT  Reserved45_IRQHandler     [WEAK]
276                EXPORT  Reserved46_IRQHandler     [WEAK]
277                EXPORT  Reserved47_IRQHandler     [WEAK]
278                EXPORT  DefaultISR                      [WEAK]
279
280Reserved16_IRQHandler
281Reserved17_IRQHandler
282Reserved18_IRQHandler
283Reserved19_IRQHandler
284Reserved20_IRQHandler
285ETMRH_IRQHandler
286LVD_LVW_IRQHandler
287IRQ_IRQHandler
288I2C0_IRQHandler
289Reserved25_IRQHandler
290SPI0_IRQHandler
291SPI1_IRQHandler
292UART0_IRQHandler
293UART1_IRQHandler
294UART2_IRQHandler
295ADC0_IRQHandler
296ACMP0_IRQHandler
297ETM0_IRQHandler
298ETM1_IRQHandler
299ETM2_IRQHandler
300RTC_IRQHandler
301ACMP1_IRQHandler
302PIT_CH0_IRQHandler
303PIT_CH1_IRQHandler
304KBI0_IRQHandler
305KBI1_IRQHandler
306Reserved42_IRQHandler
307ICS_IRQHandler
308Watchdog_IRQHandler
309Reserved45_IRQHandler
310Reserved46_IRQHandler
311Reserved47_IRQHandler
312DefaultISR
313
314                B       .
315
316                ENDP
317
318
319                ALIGN
320
321
322; User Initial Stack & Heap
323
324                IF      :DEF:__MICROLIB
325
326                EXPORT  __initial_sp
327                EXPORT  __heap_base
328                EXPORT  __heap_limit
329
330                ELSE
331
332                IMPORT  __use_two_region_memory
333                EXPORT  __user_initial_stackheap
334__user_initial_stackheap
335
336                LDR     R0, =  Heap_Mem
337                LDR     R1, =(Stack_Mem + Stack_Size)
338                LDR     R2, = (Heap_Mem +  Heap_Size)
339                LDR     R3, = Stack_Mem
340                BX      LR
341
342                ALIGN
343
344                ENDIF
345
346
347                END
348