1 /*
2 * Copyright (c) 2012, Freescale Semiconductor, Inc.
3 * All rights reserved.
4 *
5 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
6 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
7 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
8 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
9 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
10 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
11 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
12 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
13 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
14 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
15 */
16
17 // File: flexcan2_iomux_config.c
18
19 /* ------------------------------------------------------------------------------
20 * <auto-generated>
21 * This code was generated by a tool.
22 * Runtime Version:3.4.0.0
23 *
24 * Changes to this file may cause incorrect behavior and will be lost if
25 * the code is regenerated.
26 * </auto-generated>
27 * ------------------------------------------------------------------------------
28 */
29
30 #include "iomux_config.h"
31 #include "registers/regsiomuxc.h"
32
33 // Function to configure IOMUXC for flexcan2 module.
flexcan2_iomux_config(void)34 void flexcan2_iomux_config(void)
35 {
36 // Config flexcan2.FLEXCAN2_RX to pad KEY_ROW4(V5)
37 // HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_WR(0x00000000);
38 // HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_WR(0x0001B0B0);
39 // HW_IOMUXC_FLEXCAN2_RX_SELECT_INPUT_WR(0x00000000);
40 // Mux Register:
41 // IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4(0x020E0268)
42 // SION [4] - Software Input On Field Reset: DISABLED
43 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
44 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
45 // ENABLED (1) - Force input path of pad.
46 // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
47 // Select iomux modes to be used for pad.
48 // ALT0 (0) - Select instance: flexcan2 signal: FLEXCAN2_RX
49 // ALT1 (1) - Select instance: ipu1 signal: IPU1_SISG5
50 // ALT2 (2) - Select instance: usb signal: USB_OTG_PWR
51 // ALT3 (3) - Select instance: kpp signal: KEY_ROW4
52 // ALT4 (4) - Select instance: uart5 signal: UART5_CTS_B
53 // ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO15
54 HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_WR(
55 BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_SION_V(DISABLED) |
56 BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_MUX_MODE_V(ALT0));
57 // Pad Control Register:
58 // IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4(0x020E0650)
59 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
60 // DISABLED (0) - CMOS input
61 // ENABLED (1) - Schmitt trigger input
62 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PD
63 // 100K_OHM_PD (0) - 100K Ohm Pull Down
64 // 47K_OHM_PU (1) - 47K Ohm Pull Up
65 // 100K_OHM_PU (2) - 100K Ohm Pull Up
66 // 22K_OHM_PU (3) - 22K Ohm Pull Up
67 // PUE [13] - Pull / Keep Select Field Reset: PULL
68 // KEEP (0) - Keeper Enabled
69 // PULL (1) - Pull Enabled
70 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
71 // DISABLED (0) - Pull/Keeper Disabled
72 // ENABLED (1) - Pull/Keeper Enabled
73 // ODE [11] - Open Drain Enable Field Reset: DISABLED
74 // Enables open drain of the pin.
75 // DISABLED (0) - Output is CMOS.
76 // ENABLED (1) - Output is Open Drain.
77 // SPEED [7:6] - Speed Field Reset: 100MHZ
78 // RESERVED0 (0) - Reserved
79 // 50MHZ (1) - Low (50 MHz)
80 // 100MHZ (2) - Medium (100 MHz)
81 // 200MHZ (3) - Maximum (200 MHz)
82 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
83 // HIZ (0) - HI-Z
84 // 240_OHM (1) - 240 Ohm
85 // 120_OHM (2) - 120 Ohm
86 // 80_OHM (3) - 80 Ohm
87 // 60_OHM (4) - 60 Ohm
88 // 48_OHM (5) - 48 Ohm
89 // 40_OHM (6) - 40 Ohm
90 // 34_OHM (7) - 34 Ohm
91 // SRE [0] - Slew Rate Field Reset: SLOW
92 // Slew rate control.
93 // SLOW (0) - Slow Slew Rate
94 // FAST (1) - Fast Slew Rate
95 HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_WR(
96 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_HYS_V(ENABLED) |
97 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUS_V(100K_OHM_PU) |
98 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUE_V(PULL) |
99 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PKE_V(ENABLED) |
100 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_ODE_V(DISABLED) |
101 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SPEED_V(100MHZ) |
102 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_DSE_V(40_OHM) |
103 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SRE_V(SLOW));
104 // Pad KEY_ROW4 is involved in Daisy Chain.
105 // Input Select Register:
106 // IOMUXC_FLEXCAN2_RX_SELECT_INPUT(0x020E07CC)
107 // DAISY [0] - MUX Mode Select Field Reset: KEY_ROW4_ALT0
108 // Selecting Pads Involved in Daisy Chain.
109 // KEY_ROW4_ALT0 (0) - Select signal flexcan2 FLEXCAN2_RX as input from pad KEY_ROW4(ALT0).
110 // SD3_DATA1_ALT2 (1) - Select signal flexcan2 FLEXCAN2_RX as input from pad SD3_DATA1(ALT2).
111 HW_IOMUXC_FLEXCAN2_RX_SELECT_INPUT_WR(
112 BF_IOMUXC_FLEXCAN2_RX_SELECT_INPUT_DAISY_V(KEY_ROW4_ALT0));
113
114 // Config flexcan2.FLEXCAN2_TX to pad KEY_COL4(T6)
115 // HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_WR(0x00000000);
116 // HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_WR(0x0001B0B0);
117 // Mux Register:
118 // IOMUXC_SW_MUX_CTL_PAD_KEY_COL4(0x020E0254)
119 // SION [4] - Software Input On Field Reset: DISABLED
120 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
121 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
122 // ENABLED (1) - Force input path of pad.
123 // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
124 // Select iomux modes to be used for pad.
125 // ALT0 (0) - Select instance: flexcan2 signal: FLEXCAN2_TX
126 // ALT1 (1) - Select instance: ipu1 signal: IPU1_SISG4
127 // ALT2 (2) - Select instance: usb signal: USB_OTG_OC
128 // ALT3 (3) - Select instance: kpp signal: KEY_COL4
129 // ALT4 (4) - Select instance: uart5 signal: UART5_RTS_B
130 // ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO14
131 HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_WR(
132 BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_SION_V(DISABLED) |
133 BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_MUX_MODE_V(ALT0));
134 // Pad Control Register:
135 // IOMUXC_SW_PAD_CTL_PAD_KEY_COL4(0x020E063C)
136 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
137 // DISABLED (0) - CMOS input
138 // ENABLED (1) - Schmitt trigger input
139 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
140 // 100K_OHM_PD (0) - 100K Ohm Pull Down
141 // 47K_OHM_PU (1) - 47K Ohm Pull Up
142 // 100K_OHM_PU (2) - 100K Ohm Pull Up
143 // 22K_OHM_PU (3) - 22K Ohm Pull Up
144 // PUE [13] - Pull / Keep Select Field Reset: PULL
145 // KEEP (0) - Keeper Enabled
146 // PULL (1) - Pull Enabled
147 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
148 // DISABLED (0) - Pull/Keeper Disabled
149 // ENABLED (1) - Pull/Keeper Enabled
150 // ODE [11] - Open Drain Enable Field Reset: DISABLED
151 // Enables open drain of the pin.
152 // DISABLED (0) - Output is CMOS.
153 // ENABLED (1) - Output is Open Drain.
154 // SPEED [7:6] - Speed Field Reset: 100MHZ
155 // RESERVED0 (0) - Reserved
156 // 50MHZ (1) - Low (50 MHz)
157 // 100MHZ (2) - Medium (100 MHz)
158 // 200MHZ (3) - Maximum (200 MHz)
159 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
160 // HIZ (0) - HI-Z
161 // 240_OHM (1) - 240 Ohm
162 // 120_OHM (2) - 120 Ohm
163 // 80_OHM (3) - 80 Ohm
164 // 60_OHM (4) - 60 Ohm
165 // 48_OHM (5) - 48 Ohm
166 // 40_OHM (6) - 40 Ohm
167 // 34_OHM (7) - 34 Ohm
168 // SRE [0] - Slew Rate Field Reset: SLOW
169 // Slew rate control.
170 // SLOW (0) - Slow Slew Rate
171 // FAST (1) - Fast Slew Rate
172 HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_WR(
173 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_HYS_V(ENABLED) |
174 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUS_V(100K_OHM_PU) |
175 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUE_V(PULL) |
176 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PKE_V(ENABLED) |
177 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_ODE_V(DISABLED) |
178 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SPEED_V(100MHZ) |
179 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_DSE_V(40_OHM) |
180 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SRE_V(SLOW));
181 }
182