1 /*
2 * Copyright (c) 2012, Freescale Semiconductor, Inc.
3 * All rights reserved.
4 *
5 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
6 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
7 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
8 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
9 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
10 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
11 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
12 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
13 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
14 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
15 */
16
17 // File: gpio5_iomux_config.c
18
19 /* ------------------------------------------------------------------------------
20 * <auto-generated>
21 * This code was generated by a tool.
22 * Runtime Version:3.4.0.0
23 *
24 * Changes to this file may cause incorrect behavior and will be lost if
25 * the code is regenerated.
26 * </auto-generated>
27 * ------------------------------------------------------------------------------
28 */
29
30 #include "iomux_config.h"
31 #include "registers/regsiomuxc.h"
32
33 // Function to configure IOMUXC for gpio5 module.
gpio5_iomux_config(void)34 void gpio5_iomux_config(void)
35 {
36 // Config gpio5.GPIO5_IO04 to pad EIM_ADDR24(F25)
37 // EIMD18_I2C3_STEER
38 // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_WR(0x00000005);
39 // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_WR(0x0000B0B1);
40 // Mux Register:
41 // IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24(0x020E0130)
42 // SION [4] - Software Input On Field Reset: DISABLED
43 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
44 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
45 // ENABLED (1) - Force input path of pad.
46 // MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
47 // Select iomux modes to be used for pad.
48 // ALT0 (0) - Select instance: eim signal: EIM_ADDR24
49 // ALT1 (1) - Select instance: ipu1 signal: IPU1_DISP1_DATA19
50 // ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI1_DATA19
51 // ALT4 (4) - Select instance: ipu1 signal: IPU1_SISG2
52 // ALT5 (5) - Select instance: gpio5 signal: GPIO5_IO04
53 // ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG24
54 // ALT8 (8) - Select instance: epdc signal: EPDC_GDRL
55 HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_WR(
56 BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_SION_V(DISABLED) |
57 BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_MUX_MODE_V(ALT5));
58 // Pad Control Register:
59 // IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24(0x020E0500)
60 // HYS [16] - Hysteresis Enable Field Reset: DISABLED
61 // DISABLED (0) - CMOS input
62 // ENABLED (1) - Schmitt trigger input
63 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
64 // 100K_OHM_PD (0) - 100K Ohm Pull Down
65 // 47K_OHM_PU (1) - 47K Ohm Pull Up
66 // 100K_OHM_PU (2) - 100K Ohm Pull Up
67 // 22K_OHM_PU (3) - 22K Ohm Pull Up
68 // PUE [13] - Pull / Keep Select Field Reset: PULL
69 // KEEP (0) - Keeper Enabled
70 // PULL (1) - Pull Enabled
71 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
72 // DISABLED (0) - Pull/Keeper Disabled
73 // ENABLED (1) - Pull/Keeper Enabled
74 // ODE [11] - Open Drain Enable Field Reset: DISABLED
75 // Enables open drain of the pin.
76 // DISABLED (0) - Output is CMOS.
77 // ENABLED (1) - Output is Open Drain.
78 // SPEED [7:6] - Speed Field Reset: 100MHZ
79 // RESERVED0 (0) - Reserved
80 // 50MHZ (1) - Low (50 MHz)
81 // 100MHZ (2) - Medium (100 MHz)
82 // 200MHZ (3) - Maximum (200 MHz)
83 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
84 // HIZ (0) - HI-Z
85 // 240_OHM (1) - 240 Ohm
86 // 120_OHM (2) - 120 Ohm
87 // 80_OHM (3) - 80 Ohm
88 // 60_OHM (4) - 60 Ohm
89 // 48_OHM (5) - 48 Ohm
90 // 40_OHM (6) - 40 Ohm
91 // 34_OHM (7) - 34 Ohm
92 // SRE [0] - Slew Rate Field Reset: FAST
93 // Slew rate control.
94 // SLOW (0) - Slow Slew Rate
95 // FAST (1) - Fast Slew Rate
96 HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_WR(
97 BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_HYS_V(DISABLED) |
98 BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PUS_V(100K_OHM_PU) |
99 BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PUE_V(PULL) |
100 BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PKE_V(ENABLED) |
101 BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_ODE_V(DISABLED) |
102 BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_SPEED_V(100MHZ) |
103 BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_DSE_V(40_OHM) |
104 BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_SRE_V(FAST));
105
106 // Config gpio5.GPIO5_IO14 to pad DISP0_DATA20(U22)
107 // HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_WR(0x00000005);
108 // HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_WR(0x0001B0B0);
109 // Mux Register:
110 // IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20(0x020E00E4)
111 // SION [4] - Software Input On Field Reset: DISABLED
112 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
113 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
114 // ENABLED (1) - Force input path of pad.
115 // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
116 // Select iomux modes to be used for pad.
117 // ALT0 (0) - Select instance: ipu1 signal: IPU1_DISP0_DATA20
118 // ALT1 (1) - Select instance: lcd signal: LCD_DATA20
119 // ALT2 (2) - Select instance: ecspi1 signal: ECSPI1_SCLK
120 // ALT3 (3) - Select instance: audmux signal: AUD4_TXC
121 // ALT5 (5) - Select instance: gpio5 signal: GPIO5_IO14
122 HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_WR(
123 BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_SION_V(DISABLED) |
124 BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_MUX_MODE_V(ALT5));
125 // Pad Control Register:
126 // IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20(0x020E03F8)
127 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
128 // DISABLED (0) - CMOS input
129 // ENABLED (1) - Schmitt trigger input
130 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
131 // 100K_OHM_PD (0) - 100K Ohm Pull Down
132 // 47K_OHM_PU (1) - 47K Ohm Pull Up
133 // 100K_OHM_PU (2) - 100K Ohm Pull Up
134 // 22K_OHM_PU (3) - 22K Ohm Pull Up
135 // PUE [13] - Pull / Keep Select Field Reset: PULL
136 // KEEP (0) - Keeper Enabled
137 // PULL (1) - Pull Enabled
138 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
139 // DISABLED (0) - Pull/Keeper Disabled
140 // ENABLED (1) - Pull/Keeper Enabled
141 // ODE [11] - Open Drain Enable Field Reset: DISABLED
142 // Enables open drain of the pin.
143 // DISABLED (0) - Output is CMOS.
144 // ENABLED (1) - Output is Open Drain.
145 // SPEED [7:6] - Speed Field Reset: 100MHZ
146 // RESERVED0 (0) - Reserved
147 // 50MHZ (1) - Low (50 MHz)
148 // 100MHZ (2) - Medium (100 MHz)
149 // 200MHZ (3) - Maximum (200 MHz)
150 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
151 // HIZ (0) - HI-Z
152 // 240_OHM (1) - 240 Ohm
153 // 120_OHM (2) - 120 Ohm
154 // 80_OHM (3) - 80 Ohm
155 // 60_OHM (4) - 60 Ohm
156 // 48_OHM (5) - 48 Ohm
157 // 40_OHM (6) - 40 Ohm
158 // 34_OHM (7) - 34 Ohm
159 // SRE [0] - Slew Rate Field Reset: SLOW
160 // Slew rate control.
161 // SLOW (0) - Slow Slew Rate
162 // FAST (1) - Fast Slew Rate
163 HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_WR(
164 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_HYS_V(ENABLED) |
165 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUS_V(100K_OHM_PU) |
166 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUE_V(PULL) |
167 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PKE_V(ENABLED) |
168 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_ODE_V(DISABLED) |
169 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SPEED_V(100MHZ) |
170 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_DSE_V(40_OHM) |
171 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SRE_V(SLOW));
172
173 // Config gpio5.GPIO5_IO15 to pad DISP0_DATA21(T20)
174 // HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_WR(0x00000005);
175 // HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_WR(0x0001B0B0);
176 // Mux Register:
177 // IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21(0x020E00E8)
178 // SION [4] - Software Input On Field Reset: DISABLED
179 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
180 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
181 // ENABLED (1) - Force input path of pad.
182 // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
183 // Select iomux modes to be used for pad.
184 // ALT0 (0) - Select instance: ipu1 signal: IPU1_DISP0_DATA21
185 // ALT1 (1) - Select instance: lcd signal: LCD_DATA21
186 // ALT2 (2) - Select instance: ecspi1 signal: ECSPI1_MOSI
187 // ALT3 (3) - Select instance: audmux signal: AUD4_TXD
188 // ALT5 (5) - Select instance: gpio5 signal: GPIO5_IO15
189 HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_WR(
190 BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_SION_V(DISABLED) |
191 BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_MUX_MODE_V(ALT5));
192 // Pad Control Register:
193 // IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21(0x020E03FC)
194 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
195 // DISABLED (0) - CMOS input
196 // ENABLED (1) - Schmitt trigger input
197 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
198 // 100K_OHM_PD (0) - 100K Ohm Pull Down
199 // 47K_OHM_PU (1) - 47K Ohm Pull Up
200 // 100K_OHM_PU (2) - 100K Ohm Pull Up
201 // 22K_OHM_PU (3) - 22K Ohm Pull Up
202 // PUE [13] - Pull / Keep Select Field Reset: PULL
203 // KEEP (0) - Keeper Enabled
204 // PULL (1) - Pull Enabled
205 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
206 // DISABLED (0) - Pull/Keeper Disabled
207 // ENABLED (1) - Pull/Keeper Enabled
208 // ODE [11] - Open Drain Enable Field Reset: DISABLED
209 // Enables open drain of the pin.
210 // DISABLED (0) - Output is CMOS.
211 // ENABLED (1) - Output is Open Drain.
212 // SPEED [7:6] - Speed Field Reset: 100MHZ
213 // RESERVED0 (0) - Reserved
214 // 50MHZ (1) - Low (50 MHz)
215 // 100MHZ (2) - Medium (100 MHz)
216 // 200MHZ (3) - Maximum (200 MHz)
217 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
218 // HIZ (0) - HI-Z
219 // 240_OHM (1) - 240 Ohm
220 // 120_OHM (2) - 120 Ohm
221 // 80_OHM (3) - 80 Ohm
222 // 60_OHM (4) - 60 Ohm
223 // 48_OHM (5) - 48 Ohm
224 // 40_OHM (6) - 40 Ohm
225 // 34_OHM (7) - 34 Ohm
226 // SRE [0] - Slew Rate Field Reset: SLOW
227 // Slew rate control.
228 // SLOW (0) - Slow Slew Rate
229 // FAST (1) - Fast Slew Rate
230 HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_WR(
231 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_HYS_V(ENABLED) |
232 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PUS_V(100K_OHM_PU) |
233 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PUE_V(PULL) |
234 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PKE_V(ENABLED) |
235 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_ODE_V(DISABLED) |
236 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_SPEED_V(100MHZ) |
237 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_DSE_V(40_OHM) |
238 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_SRE_V(SLOW));
239
240 // Config gpio5.GPIO5_IO16 to pad DISP0_DATA22(V24)
241 // HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_WR(0x00000005);
242 // HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_WR(0x0001B0B0);
243 // Mux Register:
244 // IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22(0x020E00EC)
245 // SION [4] - Software Input On Field Reset: DISABLED
246 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
247 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
248 // ENABLED (1) - Force input path of pad.
249 // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
250 // Select iomux modes to be used for pad.
251 // ALT0 (0) - Select instance: ipu1 signal: IPU1_DISP0_DATA22
252 // ALT1 (1) - Select instance: lcd signal: LCD_DATA22
253 // ALT2 (2) - Select instance: ecspi1 signal: ECSPI1_MISO
254 // ALT3 (3) - Select instance: audmux signal: AUD4_TXFS
255 // ALT5 (5) - Select instance: gpio5 signal: GPIO5_IO16
256 HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_WR(
257 BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_SION_V(DISABLED) |
258 BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_MUX_MODE_V(ALT5));
259 // Pad Control Register:
260 // IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22(0x020E0400)
261 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
262 // DISABLED (0) - CMOS input
263 // ENABLED (1) - Schmitt trigger input
264 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
265 // 100K_OHM_PD (0) - 100K Ohm Pull Down
266 // 47K_OHM_PU (1) - 47K Ohm Pull Up
267 // 100K_OHM_PU (2) - 100K Ohm Pull Up
268 // 22K_OHM_PU (3) - 22K Ohm Pull Up
269 // PUE [13] - Pull / Keep Select Field Reset: PULL
270 // KEEP (0) - Keeper Enabled
271 // PULL (1) - Pull Enabled
272 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
273 // DISABLED (0) - Pull/Keeper Disabled
274 // ENABLED (1) - Pull/Keeper Enabled
275 // ODE [11] - Open Drain Enable Field Reset: DISABLED
276 // Enables open drain of the pin.
277 // DISABLED (0) - Output is CMOS.
278 // ENABLED (1) - Output is Open Drain.
279 // SPEED [7:6] - Speed Field Reset: 100MHZ
280 // RESERVED0 (0) - Reserved
281 // 50MHZ (1) - Low (50 MHz)
282 // 100MHZ (2) - Medium (100 MHz)
283 // 200MHZ (3) - Maximum (200 MHz)
284 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
285 // HIZ (0) - HI-Z
286 // 240_OHM (1) - 240 Ohm
287 // 120_OHM (2) - 120 Ohm
288 // 80_OHM (3) - 80 Ohm
289 // 60_OHM (4) - 60 Ohm
290 // 48_OHM (5) - 48 Ohm
291 // 40_OHM (6) - 40 Ohm
292 // 34_OHM (7) - 34 Ohm
293 // SRE [0] - Slew Rate Field Reset: SLOW
294 // Slew rate control.
295 // SLOW (0) - Slow Slew Rate
296 // FAST (1) - Fast Slew Rate
297 HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_WR(
298 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_HYS_V(ENABLED) |
299 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PUS_V(100K_OHM_PU) |
300 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PUE_V(PULL) |
301 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PKE_V(ENABLED) |
302 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_ODE_V(DISABLED) |
303 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_SPEED_V(100MHZ) |
304 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_DSE_V(40_OHM) |
305 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_SRE_V(SLOW));
306
307 // Config gpio5.GPIO5_IO17 to pad DISP0_DATA23(W24)
308 // HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_WR(0x00000005);
309 // HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_WR(0x0001B0B0);
310 // Mux Register:
311 // IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23(0x020E00F0)
312 // SION [4] - Software Input On Field Reset: DISABLED
313 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
314 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
315 // ENABLED (1) - Force input path of pad.
316 // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
317 // Select iomux modes to be used for pad.
318 // ALT0 (0) - Select instance: ipu1 signal: IPU1_DISP0_DATA23
319 // ALT1 (1) - Select instance: lcd signal: LCD_DATA23
320 // ALT2 (2) - Select instance: ecspi1 signal: ECSPI1_SS0
321 // ALT3 (3) - Select instance: audmux signal: AUD4_RXD
322 // ALT5 (5) - Select instance: gpio5 signal: GPIO5_IO17
323 HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_WR(
324 BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_SION_V(DISABLED) |
325 BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_MUX_MODE_V(ALT5));
326 // Pad Control Register:
327 // IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23(0x020E0404)
328 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
329 // DISABLED (0) - CMOS input
330 // ENABLED (1) - Schmitt trigger input
331 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
332 // 100K_OHM_PD (0) - 100K Ohm Pull Down
333 // 47K_OHM_PU (1) - 47K Ohm Pull Up
334 // 100K_OHM_PU (2) - 100K Ohm Pull Up
335 // 22K_OHM_PU (3) - 22K Ohm Pull Up
336 // PUE [13] - Pull / Keep Select Field Reset: PULL
337 // KEEP (0) - Keeper Enabled
338 // PULL (1) - Pull Enabled
339 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
340 // DISABLED (0) - Pull/Keeper Disabled
341 // ENABLED (1) - Pull/Keeper Enabled
342 // ODE [11] - Open Drain Enable Field Reset: DISABLED
343 // Enables open drain of the pin.
344 // DISABLED (0) - Output is CMOS.
345 // ENABLED (1) - Output is Open Drain.
346 // SPEED [7:6] - Speed Field Reset: 100MHZ
347 // RESERVED0 (0) - Reserved
348 // 50MHZ (1) - Low (50 MHz)
349 // 100MHZ (2) - Medium (100 MHz)
350 // 200MHZ (3) - Maximum (200 MHz)
351 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
352 // HIZ (0) - HI-Z
353 // 240_OHM (1) - 240 Ohm
354 // 120_OHM (2) - 120 Ohm
355 // 80_OHM (3) - 80 Ohm
356 // 60_OHM (4) - 60 Ohm
357 // 48_OHM (5) - 48 Ohm
358 // 40_OHM (6) - 40 Ohm
359 // 34_OHM (7) - 34 Ohm
360 // SRE [0] - Slew Rate Field Reset: SLOW
361 // Slew rate control.
362 // SLOW (0) - Slow Slew Rate
363 // FAST (1) - Fast Slew Rate
364 HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_WR(
365 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_HYS_V(ENABLED) |
366 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PUS_V(100K_OHM_PU) |
367 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PUE_V(PULL) |
368 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PKE_V(ENABLED) |
369 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_ODE_V(DISABLED) |
370 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_SPEED_V(100MHZ) |
371 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_DSE_V(40_OHM) |
372 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_SRE_V(SLOW));
373
374 // Config gpio5.GPIO5_IO20 to pad CSI0_DATA_EN(P3)
375 // HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_WR(0x00000005);
376 // HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_WR(0x0001B0B0);
377 // Mux Register:
378 // IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN(0x020E008C)
379 // SION [4] - Software Input On Field Reset: DISABLED
380 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
381 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
382 // ENABLED (1) - Force input path of pad.
383 // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
384 // Select iomux modes to be used for pad.
385 // ALT0 (0) - Select instance: ipu1 signal: IPU1_CSI0_DATA_EN
386 // ALT1 (1) - Select instance: eim signal: EIM_DATA00
387 // ALT5 (5) - Select instance: gpio5 signal: GPIO5_IO20
388 // ALT7 (7) - Select instance: arm signal: ARM_TRACE_CLK
389 HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_WR(
390 BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_SION_V(DISABLED) |
391 BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_MUX_MODE_V(ALT5));
392 // Pad Control Register:
393 // IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN(0x020E03A0)
394 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
395 // DISABLED (0) - CMOS input
396 // ENABLED (1) - Schmitt trigger input
397 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
398 // 100K_OHM_PD (0) - 100K Ohm Pull Down
399 // 47K_OHM_PU (1) - 47K Ohm Pull Up
400 // 100K_OHM_PU (2) - 100K Ohm Pull Up
401 // 22K_OHM_PU (3) - 22K Ohm Pull Up
402 // PUE [13] - Pull / Keep Select Field Reset: PULL
403 // KEEP (0) - Keeper Enabled
404 // PULL (1) - Pull Enabled
405 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
406 // DISABLED (0) - Pull/Keeper Disabled
407 // ENABLED (1) - Pull/Keeper Enabled
408 // ODE [11] - Open Drain Enable Field Reset: DISABLED
409 // Enables open drain of the pin.
410 // DISABLED (0) - Output is CMOS.
411 // ENABLED (1) - Output is Open Drain.
412 // SPEED [7:6] - Speed Field Reset: 100MHZ
413 // RESERVED0 (0) - Reserved
414 // 50MHZ (1) - Low (50 MHz)
415 // 100MHZ (2) - Medium (100 MHz)
416 // 200MHZ (3) - Maximum (200 MHz)
417 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
418 // HIZ (0) - HI-Z
419 // 240_OHM (1) - 240 Ohm
420 // 120_OHM (2) - 120 Ohm
421 // 80_OHM (3) - 80 Ohm
422 // 60_OHM (4) - 60 Ohm
423 // 48_OHM (5) - 48 Ohm
424 // 40_OHM (6) - 40 Ohm
425 // 34_OHM (7) - 34 Ohm
426 // SRE [0] - Slew Rate Field Reset: SLOW
427 // Slew rate control.
428 // SLOW (0) - Slow Slew Rate
429 // FAST (1) - Fast Slew Rate
430 HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_WR(
431 BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_HYS_V(ENABLED) |
432 BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PUS_V(100K_OHM_PU) |
433 BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PUE_V(PULL) |
434 BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PKE_V(ENABLED) |
435 BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_ODE_V(DISABLED) |
436 BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_SPEED_V(100MHZ) |
437 BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_DSE_V(40_OHM) |
438 BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_SRE_V(SLOW));
439 }
440