1 /*
2 * Copyright (c) 2012, Freescale Semiconductor, Inc.
3 * All rights reserved.
4 *
5 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
6 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
7 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
8 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
9 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
10 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
11 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
12 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
13 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
14 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
15 */
16
17 // File: gpio6_iomux_config.c
18
19 /* ------------------------------------------------------------------------------
20 * <auto-generated>
21 * This code was generated by a tool.
22 * Runtime Version:3.4.0.0
23 *
24 * Changes to this file may cause incorrect behavior and will be lost if
25 * the code is regenerated.
26 * </auto-generated>
27 * ------------------------------------------------------------------------------
28 */
29
30 #include "iomux_config.h"
31 #include "registers/regsiomuxc.h"
32
33 // Function to configure IOMUXC for gpio6 module.
gpio6_iomux_config(void)34 void gpio6_iomux_config(void)
35 {
36 // Config gpio6.GPIO6_IO15 to pad NAND_CS2_B(A17)
37 // SDa_CD_B
38 // HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_WR(0x00000005);
39 // HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_WR(0x0001B0B0);
40 // Mux Register:
41 // IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B(0x020E027C)
42 // SION [4] - Software Input On Field Reset: DISABLED
43 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
44 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
45 // ENABLED (1) - Force input path of pad.
46 // MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
47 // Select iomux modes to be used for pad.
48 // ALT0 (0) - Select instance: gpmi signal: NAND_CE2_B
49 // ALT1 (1) - Select instance: ipu1 signal: IPU1_SISG0
50 // ALT2 (2) - Select instance: esai signal: ESAI_TX0
51 // ALT3 (3) - Select instance: eim signal: EIM_CRE
52 // ALT4 (4) - Select instance: ccm signal: CCM_CLKO2
53 // ALT5 (5) - Select instance: gpio6 signal: GPIO6_IO15
54 HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_WR(
55 BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_SION_V(DISABLED) |
56 BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_MUX_MODE_V(ALT5));
57 // Pad Control Register:
58 // IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B(0x020E0664)
59 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
60 // DISABLED (0) - CMOS input
61 // ENABLED (1) - Schmitt trigger input
62 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
63 // 100K_OHM_PD (0) - 100K Ohm Pull Down
64 // 47K_OHM_PU (1) - 47K Ohm Pull Up
65 // 100K_OHM_PU (2) - 100K Ohm Pull Up
66 // 22K_OHM_PU (3) - 22K Ohm Pull Up
67 // PUE [13] - Pull / Keep Select Field Reset: PULL
68 // KEEP (0) - Keeper Enabled
69 // PULL (1) - Pull Enabled
70 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
71 // DISABLED (0) - Pull/Keeper Disabled
72 // ENABLED (1) - Pull/Keeper Enabled
73 // ODE [11] - Open Drain Enable Field Reset: DISABLED
74 // Enables open drain of the pin.
75 // DISABLED (0) - Output is CMOS.
76 // ENABLED (1) - Output is Open Drain.
77 // SPEED [7:6] - Speed Field Reset: 100MHZ
78 // RESERVED0 (0) - Reserved
79 // 50MHZ (1) - Low (50 MHz)
80 // 100MHZ (2) - Medium (100 MHz)
81 // 200MHZ (3) - Maximum (200 MHz)
82 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
83 // HIZ (0) - HI-Z
84 // 240_OHM (1) - 240 Ohm
85 // 120_OHM (2) - 120 Ohm
86 // 80_OHM (3) - 80 Ohm
87 // 60_OHM (4) - 60 Ohm
88 // 48_OHM (5) - 48 Ohm
89 // 40_OHM (6) - 40 Ohm
90 // 34_OHM (7) - 34 Ohm
91 // SRE [0] - Slew Rate Field Reset: SLOW
92 // Slew rate control.
93 // SLOW (0) - Slow Slew Rate
94 // FAST (1) - Fast Slew Rate
95 HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_WR(
96 BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_HYS_V(ENABLED) |
97 BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PUS_V(100K_OHM_PU) |
98 BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PUE_V(PULL) |
99 BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PKE_V(ENABLED) |
100 BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_ODE_V(DISABLED) |
101 BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_SPEED_V(100MHZ) |
102 BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_DSE_V(40_OHM) |
103 BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_SRE_V(SLOW));
104
105 // Config gpio6.GPIO6_IO31 to pad EIM_BCLK(N22)
106 // ACCEL_INT1_B (or ACCEL_INT2_B pop option)
107 // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_WR(0x00000005);
108 // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_WR(0x0000B0B1);
109 // Mux Register:
110 // IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK(0x020E0138)
111 // SION [4] - Software Input On Field Reset: DISABLED
112 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
113 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
114 // ENABLED (1) - Force input path of pad.
115 // MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
116 // Select iomux modes to be used for pad.
117 // ALT0 (0) - Select instance: eim signal: EIM_BCLK
118 // ALT1 (1) - Select instance: ipu1 signal: IPU1_DI1_PIN16
119 // ALT5 (5) - Select instance: gpio6 signal: GPIO6_IO31
120 // ALT8 (8) - Select instance: epdc signal: EPDC_SDCE9
121 HW_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_WR(
122 BF_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_SION_V(DISABLED) |
123 BF_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_MUX_MODE_V(ALT5));
124 // Pad Control Register:
125 // IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK(0x020E0508)
126 // HYS [16] - Hysteresis Enable Field Reset: DISABLED
127 // DISABLED (0) - CMOS input
128 // ENABLED (1) - Schmitt trigger input
129 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
130 // 100K_OHM_PD (0) - 100K Ohm Pull Down
131 // 47K_OHM_PU (1) - 47K Ohm Pull Up
132 // 100K_OHM_PU (2) - 100K Ohm Pull Up
133 // 22K_OHM_PU (3) - 22K Ohm Pull Up
134 // PUE [13] - Pull / Keep Select Field Reset: PULL
135 // KEEP (0) - Keeper Enabled
136 // PULL (1) - Pull Enabled
137 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
138 // DISABLED (0) - Pull/Keeper Disabled
139 // ENABLED (1) - Pull/Keeper Enabled
140 // ODE [11] - Open Drain Enable Field Reset: DISABLED
141 // Enables open drain of the pin.
142 // DISABLED (0) - Output is CMOS.
143 // ENABLED (1) - Output is Open Drain.
144 // SPEED [7:6] - Speed Field Reset: 100MHZ
145 // RESERVED0 (0) - Reserved
146 // 50MHZ (1) - Low (50 MHz)
147 // 100MHZ (2) - Medium (100 MHz)
148 // 200MHZ (3) - Maximum (200 MHz)
149 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
150 // HIZ (0) - HI-Z
151 // 240_OHM (1) - 240 Ohm
152 // 120_OHM (2) - 120 Ohm
153 // 80_OHM (3) - 80 Ohm
154 // 60_OHM (4) - 60 Ohm
155 // 48_OHM (5) - 48 Ohm
156 // 40_OHM (6) - 40 Ohm
157 // 34_OHM (7) - 34 Ohm
158 // SRE [0] - Slew Rate Field Reset: FAST
159 // Slew rate control.
160 // SLOW (0) - Slow Slew Rate
161 // FAST (1) - Fast Slew Rate
162 HW_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_WR(
163 BF_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_HYS_V(DISABLED) |
164 BF_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PUS_V(100K_OHM_PU) |
165 BF_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PUE_V(PULL) |
166 BF_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PKE_V(ENABLED) |
167 BF_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_ODE_V(DISABLED) |
168 BF_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_SPEED_V(100MHZ) |
169 BF_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_DSE_V(40_OHM) |
170 BF_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_SRE_V(FAST));
171 }
172