1 /*
2 * Copyright (c) 2012, Freescale Semiconductor, Inc.
3 * All rights reserved.
4 *
5 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
6 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
7 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
8 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
9 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
10 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
11 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
12 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
13 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
14 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
15 */
16
17 // File: i2c2_iomux_config.c
18
19 /* ------------------------------------------------------------------------------
20 * <auto-generated>
21 * This code was generated by a tool.
22 * Runtime Version:3.4.0.0
23 *
24 * Changes to this file may cause incorrect behavior and will be lost if
25 * the code is regenerated.
26 * </auto-generated>
27 * ------------------------------------------------------------------------------
28 */
29
30 #include "iomux_config.h"
31 #include "registers/regsiomuxc.h"
32
33 // Function to configure IOMUXC for i2c2 module.
i2c2_iomux_config(void)34 void i2c2_iomux_config(void)
35 {
36 // Config i2c2.I2C2_SCL to pad EIM_EB2(E22)
37 // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_WR(0x00000016);
38 // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_WR(0x0001B860);
39 // HW_IOMUXC_I2C2_SCL_IN_SELECT_INPUT_WR(0x00000000);
40 // Mux Register:
41 // IOMUXC_SW_MUX_CTL_PAD_EIM_EB2(0x020E01CC)
42 // SION [4] - Software Input On Field Reset: DISABLED
43 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
44 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
45 // ENABLED (1) - Force input path of pad.
46 // MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
47 // Select iomux modes to be used for pad.
48 // ALT0 (0) - Select instance: eim signal: EIM_EB2
49 // ALT1 (1) - Select instance: ecspi1 signal: ECSPI1_SS0
50 // ALT3 (3) - Select instance: ipu1 signal: IPU1_CSI1_DATA19
51 // ALT4 (4) - Select instance: hdmi signal: HDMI_TX_DDC_SCL
52 // ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO30
53 // ALT6 (6) - Select instance: i2c2 signal: I2C2_SCL
54 // ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG30
55 // ALT8 (8) - Select instance: epdc signal: EPDC_DATA05
56 HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_WR(
57 BF_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_SION_V(ENABLED) |
58 BF_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_MUX_MODE_V(ALT6));
59 // Pad Control Register:
60 // IOMUXC_SW_PAD_CTL_PAD_EIM_EB2(0x020E059C)
61 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
62 // DISABLED (0) - CMOS input
63 // ENABLED (1) - Schmitt trigger input
64 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
65 // 100K_OHM_PD (0) - 100K Ohm Pull Down
66 // 47K_OHM_PU (1) - 47K Ohm Pull Up
67 // 100K_OHM_PU (2) - 100K Ohm Pull Up
68 // 22K_OHM_PU (3) - 22K Ohm Pull Up
69 // PUE [13] - Pull / Keep Select Field Reset: PULL
70 // KEEP (0) - Keeper Enabled
71 // PULL (1) - Pull Enabled
72 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
73 // DISABLED (0) - Pull/Keeper Disabled
74 // ENABLED (1) - Pull/Keeper Enabled
75 // ODE [11] - Open Drain Enable Field Reset: DISABLED
76 // Enables open drain of the pin.
77 // DISABLED (0) - Output is CMOS.
78 // ENABLED (1) - Output is Open Drain.
79 // SPEED [7:6] - Speed Field Reset: 100MHZ
80 // RESERVED0 (0) - Reserved
81 // 50MHZ (1) - Low (50 MHz)
82 // 100MHZ (2) - Medium (100 MHz)
83 // 200MHZ (3) - Maximum (200 MHz)
84 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
85 // HIZ (0) - HI-Z
86 // 240_OHM (1) - 240 Ohm
87 // 120_OHM (2) - 120 Ohm
88 // 80_OHM (3) - 80 Ohm
89 // 60_OHM (4) - 60 Ohm
90 // 48_OHM (5) - 48 Ohm
91 // 40_OHM (6) - 40 Ohm
92 // 34_OHM (7) - 34 Ohm
93 // SRE [0] - Slew Rate Field Reset: SLOW
94 // Slew rate control.
95 // SLOW (0) - Slow Slew Rate
96 // FAST (1) - Fast Slew Rate
97 HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_WR(
98 BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_HYS_V(ENABLED) |
99 BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PUS_V(100K_OHM_PU) |
100 BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PUE_V(PULL) |
101 BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PKE_V(ENABLED) |
102 BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_ODE_V(ENABLED) |
103 BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_SPEED_V(50MHZ) |
104 BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_DSE_V(60_OHM) |
105 BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_SRE_V(SLOW));
106 // Pad EIM_EB2 is involved in Daisy Chain.
107 // Input Select Register:
108 // IOMUXC_I2C2_SCL_IN_SELECT_INPUT(0x020E0870)
109 // DAISY [0] - MUX Mode Select Field Reset: EIM_EB2_ALT6
110 // Selecting Pads Involved in Daisy Chain.
111 // EIM_EB2_ALT6 (0) - Select signal i2c2 I2C2_SCL as input from pad EIM_EB2(ALT6).
112 // KEY_COL3_ALT4 (1) - Select signal i2c2 I2C2_SCL as input from pad KEY_COL3(ALT4).
113 HW_IOMUXC_I2C2_SCL_IN_SELECT_INPUT_WR(
114 BF_IOMUXC_I2C2_SCL_IN_SELECT_INPUT_DAISY_V(EIM_EB2_ALT6));
115
116 // Config i2c2.I2C2_SDA to pad KEY_ROW3(T7)
117 // HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_WR(0x00000014);
118 // HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_WR(0x0001B860);
119 // HW_IOMUXC_I2C2_SDA_IN_SELECT_INPUT_WR(0x00000001);
120 // Mux Register:
121 // IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3(0x020E0264)
122 // SION [4] - Software Input On Field Reset: DISABLED
123 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
124 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
125 // ENABLED (1) - Force input path of pad.
126 // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
127 // Select iomux modes to be used for pad.
128 // ALT1 (1) - Select instance: asrc signal: ASRC_EXT_CLK
129 // ALT2 (2) - Select instance: hdmi signal: HDMI_TX_DDC_SDA
130 // ALT3 (3) - Select instance: kpp signal: KEY_ROW3
131 // ALT4 (4) - Select instance: i2c2 signal: I2C2_SDA
132 // ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO13
133 // ALT6 (6) - Select instance: usdhc1 signal: SD1_VSELECT
134 HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_WR(
135 BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_SION_V(ENABLED) |
136 BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_MUX_MODE_V(ALT4));
137 // Pad Control Register:
138 // IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3(0x020E064C)
139 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
140 // DISABLED (0) - CMOS input
141 // ENABLED (1) - Schmitt trigger input
142 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
143 // 100K_OHM_PD (0) - 100K Ohm Pull Down
144 // 47K_OHM_PU (1) - 47K Ohm Pull Up
145 // 100K_OHM_PU (2) - 100K Ohm Pull Up
146 // 22K_OHM_PU (3) - 22K Ohm Pull Up
147 // PUE [13] - Pull / Keep Select Field Reset: PULL
148 // KEEP (0) - Keeper Enabled
149 // PULL (1) - Pull Enabled
150 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
151 // DISABLED (0) - Pull/Keeper Disabled
152 // ENABLED (1) - Pull/Keeper Enabled
153 // ODE [11] - Open Drain Enable Field Reset: DISABLED
154 // Enables open drain of the pin.
155 // DISABLED (0) - Output is CMOS.
156 // ENABLED (1) - Output is Open Drain.
157 // SPEED [7:6] - Speed Field Reset: 100MHZ
158 // RESERVED0 (0) - Reserved
159 // 50MHZ (1) - Low (50 MHz)
160 // 100MHZ (2) - Medium (100 MHz)
161 // 200MHZ (3) - Maximum (200 MHz)
162 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
163 // HIZ (0) - HI-Z
164 // 240_OHM (1) - 240 Ohm
165 // 120_OHM (2) - 120 Ohm
166 // 80_OHM (3) - 80 Ohm
167 // 60_OHM (4) - 60 Ohm
168 // 48_OHM (5) - 48 Ohm
169 // 40_OHM (6) - 40 Ohm
170 // 34_OHM (7) - 34 Ohm
171 // SRE [0] - Slew Rate Field Reset: SLOW
172 // Slew rate control.
173 // SLOW (0) - Slow Slew Rate
174 // FAST (1) - Fast Slew Rate
175 HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_WR(
176 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_HYS_V(ENABLED) |
177 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUS_V(100K_OHM_PU) |
178 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUE_V(PULL) |
179 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PKE_V(ENABLED) |
180 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_ODE_V(ENABLED) |
181 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SPEED_V(50MHZ) |
182 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_DSE_V(60_OHM) |
183 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SRE_V(SLOW));
184 // Pad KEY_ROW3 is involved in Daisy Chain.
185 // Input Select Register:
186 // IOMUXC_I2C2_SDA_IN_SELECT_INPUT(0x020E0874)
187 // DAISY [0] - MUX Mode Select Field Reset: EIM_DATA16_ALT6
188 // Selecting Pads Involved in Daisy Chain.
189 // EIM_DATA16_ALT6 (0) - Select signal i2c2 I2C2_SDA as input from pad EIM_DATA16(ALT6).
190 // KEY_ROW3_ALT4 (1) - Select signal i2c2 I2C2_SDA as input from pad KEY_ROW3(ALT4).
191 HW_IOMUXC_I2C2_SDA_IN_SELECT_INPUT_WR(
192 BF_IOMUXC_I2C2_SDA_IN_SELECT_INPUT_DAISY_V(KEY_ROW3_ALT4));
193 }
194