1 /*
2 * Copyright (c) 2012, Freescale Semiconductor, Inc.
3 * All rights reserved.
4 *
5 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
6 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
7 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
8 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
9 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
10 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
11 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
12 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
13 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
14 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
15 */
16
17 // File: mlb_iomux_config.c
18
19 /* ------------------------------------------------------------------------------
20 * <auto-generated>
21 * This code was generated by a tool.
22 * Runtime Version:3.4.0.0
23 *
24 * Changes to this file may cause incorrect behavior and will be lost if
25 * the code is regenerated.
26 * </auto-generated>
27 * ------------------------------------------------------------------------------
28 */
29
30 #include "iomux_config.h"
31 #include "registers/regsiomuxc.h"
32
33 // Function to configure IOMUXC for mlb module.
mlb_iomux_config(void)34 void mlb_iomux_config(void)
35 {
36 // Config mlb.MLB_CLK to pad ENET_TX_DATA1(W20)
37 // HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_WR(0x00000000);
38 // HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_WR(0x0001B0B0);
39 // HW_IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_WR(0x00000000);
40 // Mux Register:
41 // IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1(0x020E0208)
42 // SION [4] - Software Input On Field Reset: DISABLED
43 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
44 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
45 // ENABLED (1) - Force input path of pad.
46 // MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
47 // Select iomux modes to be used for pad.
48 // ALT0 (0) - Select instance: mlb signal: MLB_CLK
49 // ALT1 (1) - Select instance: enet signal: ENET_TX_DATA1
50 // ALT2 (2) - Select instance: esai signal: ESAI_TX2_RX3
51 // ALT4 (4) - Select instance: enet signal: ENET_1588_EVENT0_IN
52 // ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO29
53 // ALT9 (9) - Select instance: i2c4 signal: I2C4_SDA
54 HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_WR(
55 BF_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_SION_V(DISABLED) |
56 BF_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_MUX_MODE_V(ALT0));
57 // Pad Control Register:
58 // IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1(0x020E05D8)
59 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
60 // DISABLED (0) - CMOS input
61 // ENABLED (1) - Schmitt trigger input
62 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
63 // 100K_OHM_PD (0) - 100K Ohm Pull Down
64 // 47K_OHM_PU (1) - 47K Ohm Pull Up
65 // 100K_OHM_PU (2) - 100K Ohm Pull Up
66 // 22K_OHM_PU (3) - 22K Ohm Pull Up
67 // PUE [13] - Pull / Keep Select Field Reset: PULL
68 // KEEP (0) - Keeper Enabled
69 // PULL (1) - Pull Enabled
70 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
71 // DISABLED (0) - Pull/Keeper Disabled
72 // ENABLED (1) - Pull/Keeper Enabled
73 // ODE [11] - Open Drain Enable Field Reset: DISABLED
74 // Enables open drain of the pin.
75 // DISABLED (0) - Output is CMOS.
76 // ENABLED (1) - Output is Open Drain.
77 // SPEED [7:6] - Speed Field Reset: 100MHZ
78 // RESERVED0 (0) - Reserved
79 // 50MHZ (1) - Low (50 MHz)
80 // 100MHZ (2) - Medium (100 MHz)
81 // 200MHZ (3) - Maximum (200 MHz)
82 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
83 // HIZ (0) - HI-Z
84 // 240_OHM (1) - 240 Ohm
85 // 120_OHM (2) - 120 Ohm
86 // 80_OHM (3) - 80 Ohm
87 // 60_OHM (4) - 60 Ohm
88 // 48_OHM (5) - 48 Ohm
89 // 40_OHM (6) - 40 Ohm
90 // 34_OHM (7) - 34 Ohm
91 // SRE [0] - Slew Rate Field Reset: SLOW
92 // Slew rate control.
93 // SLOW (0) - Slow Slew Rate
94 // FAST (1) - Fast Slew Rate
95 HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_WR(
96 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_HYS_V(ENABLED) |
97 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PUS_V(100K_OHM_PU) |
98 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PUE_V(PULL) |
99 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PKE_V(ENABLED) |
100 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_ODE_V(DISABLED) |
101 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_SPEED_V(100MHZ) |
102 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_DSE_V(40_OHM) |
103 BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_SRE_V(SLOW));
104 // Pad ENET_TX_DATA1 is involved in Daisy Chain.
105 // Input Select Register:
106 // IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT(0x020E08DC)
107 // DAISY [0] - MUX Mode Select Field Reset: ENET_TX_DATA1_ALT0
108 // Selecting Pads Involved in Daisy Chain.
109 // ENET_TX_DATA1_ALT0 (0) - Select signal mlb MLB_CLK as input from pad ENET_TX_DATA1(ALT0).
110 // GPIO03_ALT7 (1) - Select signal mlb MLB_CLK as input from pad GPIO03(ALT7).
111 HW_IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_WR(
112 BF_IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_DAISY_V(ENET_TX_DATA1_ALT0));
113
114 // Config mlb.MLB_DATA to pad GPIO02(T1)
115 // HW_IOMUXC_SW_MUX_CTL_PAD_GPIO02_WR(0x00000007);
116 // HW_IOMUXC_SW_PAD_CTL_PAD_GPIO02_WR(0x0001B0B0);
117 // HW_IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_WR(0x00000000);
118 // Mux Register:
119 // IOMUXC_SW_MUX_CTL_PAD_GPIO02(0x020E0224)
120 // SION [4] - Software Input On Field Reset: DISABLED
121 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
122 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
123 // ENABLED (1) - Force input path of pad.
124 // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
125 // Select iomux modes to be used for pad.
126 // ALT0 (0) - Select instance: esai signal: ESAI_TX_FS
127 // ALT2 (2) - Select instance: kpp signal: KEY_ROW6
128 // ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO02
129 // ALT6 (6) - Select instance: usdhc2 signal: SD2_WP
130 // ALT7 (7) - Select instance: mlb signal: MLB_DATA
131 HW_IOMUXC_SW_MUX_CTL_PAD_GPIO02_WR(
132 BF_IOMUXC_SW_MUX_CTL_PAD_GPIO02_SION_V(DISABLED) |
133 BF_IOMUXC_SW_MUX_CTL_PAD_GPIO02_MUX_MODE_V(ALT7));
134 // Pad Control Register:
135 // IOMUXC_SW_PAD_CTL_PAD_GPIO02(0x020E05F4)
136 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
137 // DISABLED (0) - CMOS input
138 // ENABLED (1) - Schmitt trigger input
139 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
140 // 100K_OHM_PD (0) - 100K Ohm Pull Down
141 // 47K_OHM_PU (1) - 47K Ohm Pull Up
142 // 100K_OHM_PU (2) - 100K Ohm Pull Up
143 // 22K_OHM_PU (3) - 22K Ohm Pull Up
144 // PUE [13] - Pull / Keep Select Field Reset: PULL
145 // KEEP (0) - Keeper Enabled
146 // PULL (1) - Pull Enabled
147 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
148 // DISABLED (0) - Pull/Keeper Disabled
149 // ENABLED (1) - Pull/Keeper Enabled
150 // ODE [11] - Open Drain Enable Field Reset: DISABLED
151 // Enables open drain of the pin.
152 // DISABLED (0) - Output is CMOS.
153 // ENABLED (1) - Output is Open Drain.
154 // SPEED [7:6] - Speed Field Reset: 100MHZ
155 // RESERVED0 (0) - Reserved
156 // 50MHZ (1) - Low (50 MHz)
157 // 100MHZ (2) - Medium (100 MHz)
158 // 200MHZ (3) - Maximum (200 MHz)
159 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
160 // HIZ (0) - HI-Z
161 // 240_OHM (1) - 240 Ohm
162 // 120_OHM (2) - 120 Ohm
163 // 80_OHM (3) - 80 Ohm
164 // 60_OHM (4) - 60 Ohm
165 // 48_OHM (5) - 48 Ohm
166 // 40_OHM (6) - 40 Ohm
167 // 34_OHM (7) - 34 Ohm
168 // SRE [0] - Slew Rate Field Reset: SLOW
169 // Slew rate control.
170 // SLOW (0) - Slow Slew Rate
171 // FAST (1) - Fast Slew Rate
172 HW_IOMUXC_SW_PAD_CTL_PAD_GPIO02_WR(
173 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO02_HYS_V(ENABLED) |
174 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PUS_V(100K_OHM_PU) |
175 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PUE_V(PULL) |
176 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PKE_V(ENABLED) |
177 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO02_ODE_V(DISABLED) |
178 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO02_SPEED_V(100MHZ) |
179 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO02_DSE_V(40_OHM) |
180 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO02_SRE_V(SLOW));
181 // Pad GPIO02 is involved in Daisy Chain.
182 // Input Select Register:
183 // IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT(0x020E08E0)
184 // DAISY [0] - MUX Mode Select Field Reset: ENET_MDC_ALT0
185 // Selecting Pads Involved in Daisy Chain.
186 // ENET_MDC_ALT0 (0) - Select signal mlb MLB_DATA as input from pad ENET_MDC(ALT0).
187 // GPIO02_ALT7 (1) - Select signal mlb MLB_DATA as input from pad GPIO02(ALT7).
188 HW_IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_WR(
189 BF_IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_DAISY_V(ENET_MDC_ALT0));
190
191 // Config mlb.MLB_SIG to pad GPIO06(T3)
192 // HW_IOMUXC_SW_MUX_CTL_PAD_GPIO06_WR(0x00000007);
193 // HW_IOMUXC_SW_PAD_CTL_PAD_GPIO06_WR(0x0001B0B0);
194 // HW_IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_WR(0x00000000);
195 // Mux Register:
196 // IOMUXC_SW_MUX_CTL_PAD_GPIO06(0x020E0234)
197 // SION [4] - Software Input On Field Reset: DISABLED
198 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
199 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
200 // ENABLED (1) - Force input path of pad.
201 // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
202 // Select iomux modes to be used for pad.
203 // ALT0 (0) - Select instance: esai signal: ESAI_TX_CLK
204 // ALT2 (2) - Select instance: i2c3 signal: I2C3_SDA
205 // ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO06
206 // ALT6 (6) - Select instance: usdhc2 signal: SD2_LCTL
207 // ALT7 (7) - Select instance: mlb signal: MLB_SIG
208 HW_IOMUXC_SW_MUX_CTL_PAD_GPIO06_WR(
209 BF_IOMUXC_SW_MUX_CTL_PAD_GPIO06_SION_V(DISABLED) |
210 BF_IOMUXC_SW_MUX_CTL_PAD_GPIO06_MUX_MODE_V(ALT7));
211 // Pad Control Register:
212 // IOMUXC_SW_PAD_CTL_PAD_GPIO06(0x020E0604)
213 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
214 // DISABLED (0) - CMOS input
215 // ENABLED (1) - Schmitt trigger input
216 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
217 // 100K_OHM_PD (0) - 100K Ohm Pull Down
218 // 47K_OHM_PU (1) - 47K Ohm Pull Up
219 // 100K_OHM_PU (2) - 100K Ohm Pull Up
220 // 22K_OHM_PU (3) - 22K Ohm Pull Up
221 // PUE [13] - Pull / Keep Select Field Reset: PULL
222 // KEEP (0) - Keeper Enabled
223 // PULL (1) - Pull Enabled
224 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
225 // DISABLED (0) - Pull/Keeper Disabled
226 // ENABLED (1) - Pull/Keeper Enabled
227 // ODE [11] - Open Drain Enable Field Reset: DISABLED
228 // Enables open drain of the pin.
229 // DISABLED (0) - Output is CMOS.
230 // ENABLED (1) - Output is Open Drain.
231 // SPEED [7:6] - Speed Field Reset: 100MHZ
232 // RESERVED0 (0) - Reserved
233 // 50MHZ (1) - Low (50 MHz)
234 // 100MHZ (2) - Medium (100 MHz)
235 // 200MHZ (3) - Maximum (200 MHz)
236 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
237 // HIZ (0) - HI-Z
238 // 240_OHM (1) - 240 Ohm
239 // 120_OHM (2) - 120 Ohm
240 // 80_OHM (3) - 80 Ohm
241 // 60_OHM (4) - 60 Ohm
242 // 48_OHM (5) - 48 Ohm
243 // 40_OHM (6) - 40 Ohm
244 // 34_OHM (7) - 34 Ohm
245 // SRE [0] - Slew Rate Field Reset: SLOW
246 // Slew rate control.
247 // SLOW (0) - Slow Slew Rate
248 // FAST (1) - Fast Slew Rate
249 HW_IOMUXC_SW_PAD_CTL_PAD_GPIO06_WR(
250 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO06_HYS_V(ENABLED) |
251 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PUS_V(100K_OHM_PU) |
252 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PUE_V(PULL) |
253 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PKE_V(ENABLED) |
254 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO06_ODE_V(DISABLED) |
255 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO06_SPEED_V(100MHZ) |
256 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO06_DSE_V(40_OHM) |
257 BF_IOMUXC_SW_PAD_CTL_PAD_GPIO06_SRE_V(SLOW));
258 // Pad GPIO06 is involved in Daisy Chain.
259 // Input Select Register:
260 // IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT(0x020E08E4)
261 // DAISY [0] - MUX Mode Select Field Reset: ENET_RX_DATA1_ALT0
262 // Selecting Pads Involved in Daisy Chain.
263 // ENET_RX_DATA1_ALT0 (0) - Select signal mlb MLB_SIG as input from pad ENET_RX_DATA1(ALT0).
264 // GPIO06_ALT7 (1) - Select signal mlb MLB_SIG as input from pad GPIO06(ALT7).
265 HW_IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_WR(
266 BF_IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_DAISY_V(ENET_RX_DATA1_ALT0));
267 }
268