1 /*
2 * Copyright (c) 2012, Freescale Semiconductor, Inc.
3 * All rights reserved.
4 *
5 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
6 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
7 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
8 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
9 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
10 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
11 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
12 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
13 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
14 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
15 */
16
17 // File: uart4_iomux_config.c
18
19 /* ------------------------------------------------------------------------------
20 * <auto-generated>
21 * This code was generated by a tool.
22 * Runtime Version:3.4.0.0
23 *
24 * Changes to this file may cause incorrect behavior and will be lost if
25 * the code is regenerated.
26 * </auto-generated>
27 * ------------------------------------------------------------------------------
28 */
29
30 #include "iomux_config.h"
31 #include "registers/regsiomuxc.h"
32
33 // Function to configure IOMUXC for uart4 module.
uart4_iomux_config(void)34 void uart4_iomux_config(void)
35 {
36 // Config uart4.UART4_RX_DATA to pad KEY_ROW0(V6)
37 // HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_WR(0x00000004);
38 // HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_WR(0x0001B0B0);
39 // HW_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_WR(0x00000003);
40 // Mux Register:
41 // IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0(0x020E0258)
42 // SION [4] - Software Input On Field Reset: DISABLED
43 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
44 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
45 // ENABLED (1) - Force input path of pad.
46 // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
47 // Select iomux modes to be used for pad.
48 // ALT0 (0) - Select instance: ecspi1 signal: ECSPI1_MOSI
49 // ALT1 (1) - Select instance: enet signal: ENET_TX_DATA3
50 // ALT2 (2) - Select instance: audmux signal: AUD5_TXD
51 // ALT3 (3) - Select instance: kpp signal: KEY_ROW0
52 // ALT4 (4) - Select instance: uart4 signal: UART4_RX_DATA
53 // ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO07
54 // ALT6 (6) - Select instance: dcic2 signal: DCIC2_OUT
55 HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_WR(
56 BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_SION_V(DISABLED) |
57 BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_MUX_MODE_V(ALT4));
58 // Pad Control Register:
59 // IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0(0x020E0640)
60 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
61 // DISABLED (0) - CMOS input
62 // ENABLED (1) - Schmitt trigger input
63 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
64 // 100K_OHM_PD (0) - 100K Ohm Pull Down
65 // 47K_OHM_PU (1) - 47K Ohm Pull Up
66 // 100K_OHM_PU (2) - 100K Ohm Pull Up
67 // 22K_OHM_PU (3) - 22K Ohm Pull Up
68 // PUE [13] - Pull / Keep Select Field Reset: PULL
69 // KEEP (0) - Keeper Enabled
70 // PULL (1) - Pull Enabled
71 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
72 // DISABLED (0) - Pull/Keeper Disabled
73 // ENABLED (1) - Pull/Keeper Enabled
74 // ODE [11] - Open Drain Enable Field Reset: DISABLED
75 // Enables open drain of the pin.
76 // DISABLED (0) - Output is CMOS.
77 // ENABLED (1) - Output is Open Drain.
78 // SPEED [7:6] - Speed Field Reset: 100MHZ
79 // RESERVED0 (0) - Reserved
80 // 50MHZ (1) - Low (50 MHz)
81 // 100MHZ (2) - Medium (100 MHz)
82 // 200MHZ (3) - Maximum (200 MHz)
83 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
84 // HIZ (0) - HI-Z
85 // 240_OHM (1) - 240 Ohm
86 // 120_OHM (2) - 120 Ohm
87 // 80_OHM (3) - 80 Ohm
88 // 60_OHM (4) - 60 Ohm
89 // 48_OHM (5) - 48 Ohm
90 // 40_OHM (6) - 40 Ohm
91 // 34_OHM (7) - 34 Ohm
92 // SRE [0] - Slew Rate Field Reset: SLOW
93 // Slew rate control.
94 // SLOW (0) - Slow Slew Rate
95 // FAST (1) - Fast Slew Rate
96 HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_WR(
97 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_HYS_V(ENABLED) |
98 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUS_V(100K_OHM_PU) |
99 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUE_V(PULL) |
100 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PKE_V(ENABLED) |
101 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_ODE_V(DISABLED) |
102 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SPEED_V(100MHZ) |
103 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_DSE_V(40_OHM) |
104 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SRE_V(SLOW));
105 // Pad KEY_ROW0 is involved in Daisy Chain.
106 // Input Select Register:
107 // IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT(0x020E0914)
108 // DAISY [1:0] - MUX Mode Select Field Reset: CSI0_DATA12_ALT3
109 // Selecting Pads Involved in Daisy Chain.
110 // CSI0_DATA12_ALT3 (0) - Select signal uart4 UART4_TX_DATA as input from pad CSI0_DATA12(ALT3).
111 // CSI0_DATA13_ALT3 (1) - Select signal uart4 UART4_RX_DATA as input from pad CSI0_DATA13(ALT3).
112 // KEY_COL0_ALT4 (2) - Select signal uart4 UART4_TX_DATA as input from pad KEY_COL0(ALT4).
113 // KEY_ROW0_ALT4 (3) - Select signal uart4 UART4_RX_DATA as input from pad KEY_ROW0(ALT4).
114 HW_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_WR(
115 BF_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_DAISY_V(KEY_ROW0_ALT4));
116
117 // Config uart4.UART4_TX_DATA to pad KEY_COL0(W5)
118 // HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_WR(0x00000004);
119 // HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_WR(0x0001B0B0);
120 // HW_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_WR(0x00000003);
121 // Mux Register:
122 // IOMUXC_SW_MUX_CTL_PAD_KEY_COL0(0x020E0244)
123 // SION [4] - Software Input On Field Reset: DISABLED
124 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
125 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
126 // ENABLED (1) - Force input path of pad.
127 // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
128 // Select iomux modes to be used for pad.
129 // ALT0 (0) - Select instance: ecspi1 signal: ECSPI1_SCLK
130 // ALT1 (1) - Select instance: enet signal: ENET_RX_DATA3
131 // ALT2 (2) - Select instance: audmux signal: AUD5_TXC
132 // ALT3 (3) - Select instance: kpp signal: KEY_COL0
133 // ALT4 (4) - Select instance: uart4 signal: UART4_TX_DATA
134 // ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO06
135 // ALT6 (6) - Select instance: dcic1 signal: DCIC1_OUT
136 HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_WR(
137 BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_SION_V(DISABLED) |
138 BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_MUX_MODE_V(ALT4));
139 // Pad Control Register:
140 // IOMUXC_SW_PAD_CTL_PAD_KEY_COL0(0x020E062C)
141 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
142 // DISABLED (0) - CMOS input
143 // ENABLED (1) - Schmitt trigger input
144 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
145 // 100K_OHM_PD (0) - 100K Ohm Pull Down
146 // 47K_OHM_PU (1) - 47K Ohm Pull Up
147 // 100K_OHM_PU (2) - 100K Ohm Pull Up
148 // 22K_OHM_PU (3) - 22K Ohm Pull Up
149 // PUE [13] - Pull / Keep Select Field Reset: PULL
150 // KEEP (0) - Keeper Enabled
151 // PULL (1) - Pull Enabled
152 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
153 // DISABLED (0) - Pull/Keeper Disabled
154 // ENABLED (1) - Pull/Keeper Enabled
155 // ODE [11] - Open Drain Enable Field Reset: DISABLED
156 // Enables open drain of the pin.
157 // DISABLED (0) - Output is CMOS.
158 // ENABLED (1) - Output is Open Drain.
159 // SPEED [7:6] - Speed Field Reset: 100MHZ
160 // RESERVED0 (0) - Reserved
161 // 50MHZ (1) - Low (50 MHz)
162 // 100MHZ (2) - Medium (100 MHz)
163 // 200MHZ (3) - Maximum (200 MHz)
164 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
165 // HIZ (0) - HI-Z
166 // 240_OHM (1) - 240 Ohm
167 // 120_OHM (2) - 120 Ohm
168 // 80_OHM (3) - 80 Ohm
169 // 60_OHM (4) - 60 Ohm
170 // 48_OHM (5) - 48 Ohm
171 // 40_OHM (6) - 40 Ohm
172 // 34_OHM (7) - 34 Ohm
173 // SRE [0] - Slew Rate Field Reset: SLOW
174 // Slew rate control.
175 // SLOW (0) - Slow Slew Rate
176 // FAST (1) - Fast Slew Rate
177 HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_WR(
178 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_HYS_V(ENABLED) |
179 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUS_V(100K_OHM_PU) |
180 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUE_V(PULL) |
181 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PKE_V(ENABLED) |
182 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_ODE_V(DISABLED) |
183 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SPEED_V(100MHZ) |
184 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_DSE_V(40_OHM) |
185 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SRE_V(SLOW));
186 // Pad KEY_COL0 is involved in Daisy Chain.
187 // Input Select Register:
188 // IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT(0x020E0914)
189 // DAISY [1:0] - MUX Mode Select Field Reset: CSI0_DATA12_ALT3
190 // Selecting Pads Involved in Daisy Chain.
191 // CSI0_DATA12_ALT3 (0) - Select signal uart4 UART4_TX_DATA as input from pad CSI0_DATA12(ALT3).
192 // CSI0_DATA13_ALT3 (1) - Select signal uart4 UART4_RX_DATA as input from pad CSI0_DATA13(ALT3).
193 // KEY_COL0_ALT4 (2) - Select signal uart4 UART4_TX_DATA as input from pad KEY_COL0(ALT4).
194 // KEY_ROW0_ALT4 (3) - Select signal uart4 UART4_RX_DATA as input from pad KEY_ROW0(ALT4).
195 HW_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_WR(
196 BF_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_DAISY_V(KEY_ROW0_ALT4));
197 }
198