1 /*
2 * Copyright (c) 2012, Freescale Semiconductor, Inc.
3 * All rights reserved.
4 *
5 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
6 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
7 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
8 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
9 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
10 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
11 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
12 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
13 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
14 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
15 */
16
17 // File: wdog1_iomux_config.c
18
19 /* ------------------------------------------------------------------------------
20 * <auto-generated>
21 * This code was generated by a tool.
22 * Runtime Version:3.4.0.0
23 *
24 * Changes to this file may cause incorrect behavior and will be lost if
25 * the code is regenerated.
26 * </auto-generated>
27 * ------------------------------------------------------------------------------
28 */
29
30 #include "iomux_config.h"
31 #include "registers/regsiomuxc.h"
32
33 // Function to configure IOMUXC for wdog1 module.
wdog1_iomux_config(void)34 void wdog1_iomux_config(void)
35 {
36 // Config wdog1.WDOG1_B to pad DISP0_DATA08(R22)
37 // HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_WR(0x00000003);
38 // HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_WR(0x0001B0B0);
39 // Mux Register:
40 // IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08(0x020E0108)
41 // SION [4] - Software Input On Field Reset: DISABLED
42 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
43 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
44 // ENABLED (1) - Force input path of pad.
45 // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
46 // Select iomux modes to be used for pad.
47 // ALT0 (0) - Select instance: ipu1 signal: IPU1_DISP0_DATA08
48 // ALT1 (1) - Select instance: lcd signal: LCD_DATA08
49 // ALT2 (2) - Select instance: pwm1 signal: PWM1_OUT
50 // ALT3 (3) - Select instance: wdog1 signal: WDOG1_B
51 // ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO29
52 HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_WR(
53 BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_SION_V(DISABLED) |
54 BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_MUX_MODE_V(ALT3));
55 // Pad Control Register:
56 // IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08(0x020E041C)
57 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
58 // DISABLED (0) - CMOS input
59 // ENABLED (1) - Schmitt trigger input
60 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
61 // 100K_OHM_PD (0) - 100K Ohm Pull Down
62 // 47K_OHM_PU (1) - 47K Ohm Pull Up
63 // 100K_OHM_PU (2) - 100K Ohm Pull Up
64 // 22K_OHM_PU (3) - 22K Ohm Pull Up
65 // PUE [13] - Pull / Keep Select Field Reset: PULL
66 // KEEP (0) - Keeper Enabled
67 // PULL (1) - Pull Enabled
68 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
69 // DISABLED (0) - Pull/Keeper Disabled
70 // ENABLED (1) - Pull/Keeper Enabled
71 // ODE [11] - Open Drain Enable Field Reset: DISABLED
72 // Enables open drain of the pin.
73 // DISABLED (0) - Output is CMOS.
74 // ENABLED (1) - Output is Open Drain.
75 // SPEED [7:6] - Speed Field Reset: 100MHZ
76 // RESERVED0 (0) - Reserved
77 // 50MHZ (1) - Low (50 MHz)
78 // 100MHZ (2) - Medium (100 MHz)
79 // 200MHZ (3) - Maximum (200 MHz)
80 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
81 // HIZ (0) - HI-Z
82 // 240_OHM (1) - 240 Ohm
83 // 120_OHM (2) - 120 Ohm
84 // 80_OHM (3) - 80 Ohm
85 // 60_OHM (4) - 60 Ohm
86 // 48_OHM (5) - 48 Ohm
87 // 40_OHM (6) - 40 Ohm
88 // 34_OHM (7) - 34 Ohm
89 // SRE [0] - Slew Rate Field Reset: SLOW
90 // Slew rate control.
91 // SLOW (0) - Slow Slew Rate
92 // FAST (1) - Fast Slew Rate
93 HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_WR(
94 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_HYS_V(ENABLED) |
95 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PUS_V(100K_OHM_PU) |
96 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PUE_V(PULL) |
97 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PKE_V(ENABLED) |
98 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_ODE_V(DISABLED) |
99 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_SPEED_V(100MHZ) |
100 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_DSE_V(40_OHM) |
101 BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_SRE_V(SLOW));
102 }
103