1 /*
2 * Copyright (c) 2006-2018, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2018-03-22 quanzhao first version
9 */
10 #ifndef __IMX6UL_H__
11 #define __IMX6UL_H__
12
13 #include <rthw.h>
14 #include <rtthread.h>
15
16 /* SOC-relative definitions */
17 //#include "realview.h"
18 #include "gic_registers.h"
19 #include "irq_numbers.h"
20
21 /* the maximum number of gic */
22 # define ARM_GIC_MAX_NR 1
23
24 /* the maximum number of interrupts */
25 #define ARM_GIC_NR_IRQS IMX_INTERRUPT_COUNT
26
27 /* the maximum entries of the interrupt table */
28 #define MAX_HANDLERS IMX_INTERRUPT_COUNT
29
30 /* the basic constants needed by gic */
platform_get_gic_dist_base(void)31 rt_inline rt_uint32_t platform_get_gic_dist_base(void)
32 {
33 rt_uint32_t gic_base;
34 asm volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r"(gic_base));
35 return gic_base + kGICDBaseOffset;
36 }
37
platform_get_gic_cpu_base(void)38 rt_inline rt_uint32_t platform_get_gic_cpu_base(void)
39 {
40 rt_uint32_t gic_base;
41 asm volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r"(gic_base));
42 return gic_base + kGICCBaseOffset;
43 }
44
45 #define GIC_IRQ_START 0
46
47 #define GIC_ACK_INTID_MASK 0x000003ff
48
49 /* the definition needed by gic.c */
50 #define __REG32(x) (*((volatile unsigned int *)(x)))
51
52 /* keep compatible with platform SDK */
53 typedef enum {
54 CPU_0,
55 CPU_1,
56 CPU_2,
57 CPU_3,
58 } cpuid_e;
59
60 enum _gicd_sgi_filter
61 {
62 //! Forward the interrupt to the CPU interfaces specified in the @a target_list parameter.
63 kGicSgiFilter_UseTargetList = 0,
64
65 //! Forward the interrupt to all CPU interfaces except that of the processor that requested
66 //! the interrupt.
67 kGicSgiFilter_AllOtherCPUs = 1,
68
69 //! Forward the interrupt only to the CPU interface of the processor that requested the
70 //! interrupt.
71 kGicSgiFilter_OnlyThisCPU = 2
72 };
73
74 typedef void (*irq_hdlr_t) (void);
75
76 extern void rt_hw_interrupt_mask(int vector);
77 extern void rt_hw_interrupt_umask(int vector);
78 extern rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
79 void *param, const char *name);
80
register_interrupt_routine(uint32_t irq_id,irq_hdlr_t isr)81 rt_inline void register_interrupt_routine(uint32_t irq_id, irq_hdlr_t isr)
82 {
83 rt_hw_interrupt_install(irq_id, (rt_isr_handler_t)isr, NULL, "unknown");
84 }
85
enable_interrupt(uint32_t irq_id,uint32_t cpu_id,uint32_t priority)86 rt_inline void enable_interrupt(uint32_t irq_id, uint32_t cpu_id, uint32_t priority)
87 {
88 rt_hw_interrupt_umask(irq_id);
89 }
90
disable_interrupt(uint32_t irq_id,uint32_t cpu_id)91 rt_inline void disable_interrupt(uint32_t irq_id, uint32_t cpu_id)
92 {
93 rt_hw_interrupt_mask(irq_id);
94 }
95
96 #endif /* __IMX6UL_H__ */
97