1 /*
2 * Copyright (c) 2012, Freescale Semiconductor, Inc.
3 * All rights reserved.
4 *
5 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
6 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
7 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
8 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
9 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
10 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
11 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
12 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
13 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
14 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
15 */
16
17 // File: uart_iomux_config.c
18
19 /* ------------------------------------------------------------------------------
20 * <auto-generated>
21 * This code was generated by a tool.
22 * Runtime Version:3.4.0.0
23 *
24 * Changes to this file may cause incorrect behavior and will be lost if
25 * the code is regenerated.
26 * </auto-generated>
27 * ------------------------------------------------------------------------------
28 */
29
30 #include "iomux_config.h"
31 #include "registers/regsuart.h"
32 #include "iomux_register.h"
33 #include "io.h"
34 #include <assert.h>
35
36 #define MX6UL_PAD_UART1_TX_DATA__UART1_TX1 (IOMUXC_BASE_ADDR+0x084)
37 #define MX6UL_PAD_UART1_RX_DATA__UART1_RX1 (IOMUXC_BASE_ADDR+0x088)
38 #define IOMUXC_UART1_UART_RXD_MUX_SELECT_INPUT1 (IOMUXC_BASE_ADDR+0x624)
39
40 #define PIN_CFG(mux_ctl_offset, pad_ctl_offset, select_input_offset, mux_mode, daisy, pad_setting) \
41 do {\
42 writel(mux_mode, IOMUXC_BASE_ADDR + mux_ctl_offset);\
43 if (select_input_offset != 0)\
44 writel(daisy, IOMUXC_BASE_ADDR + select_input_offset);\
45 writel(pad_setting, IOMUXC_BASE_ADDR + pad_ctl_offset);\
46 } while(0);
47
48 #define MX6UL_PAD_UART1_TX_DATA__UART1_TX(p) PIN_CFG(0x0084, 0x0310, 0x0624, 0x0, 0x2, p)
49 #define MX6UL_PAD_UART1_RX_DATA__UART1_RX(p) PIN_CFG(0x0088, 0x0314, 0x0624, 0x0, 0x3, p)
50
uart1_iomux_config(void)51 void uart1_iomux_config(void)
52 {
53 /* UART1 TXD */
54 MX6UL_PAD_UART1_TX_DATA__UART1_TX(0x10b0);
55 /* UART1 RXD */
56 MX6UL_PAD_UART1_RX_DATA__UART1_RX(0x10b0);
57 }
58
uart2_iomux_config(void)59 void uart2_iomux_config(void)
60 {
61 }
62
uart3_iomux_config(void)63 void uart3_iomux_config(void)
64 {
65 }
66
uart4_iomux_config(void)67 void uart4_iomux_config(void)
68 {
69 }
70
uart5_iomux_config(void)71 void uart5_iomux_config(void)
72 {
73 }
74
uart6_iomux_config(void)75 void uart6_iomux_config(void)
76 {
77 }
78
uart7_iomux_config(void)79 void uart7_iomux_config(void)
80 {
81 }
82
uart8_iomux_config(void)83 void uart8_iomux_config(void)
84 {
85 }
86
87
uart_iomux_config(int instance)88 void uart_iomux_config(int instance)
89 {
90 switch (instance)
91 {
92 case HW_UART1:
93 return uart1_iomux_config();
94
95 case HW_UART2:
96 return uart2_iomux_config();
97
98 case HW_UART3:
99 return uart3_iomux_config();
100
101 case HW_UART4:
102 return uart4_iomux_config();
103
104 case HW_UART5:
105 return uart5_iomux_config();
106
107 case HW_UART6:
108 return uart5_iomux_config();
109
110 case HW_UART7:
111 return uart5_iomux_config();
112
113 case HW_UART8:
114 return uart5_iomux_config();
115
116 default:
117 assert(false);
118 }
119 }
120
121