1 /*
2 * Copyright (c) 2006-2023, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2009-01-05 Bernard first implementation
9 */
10
11 #include <rthw.h>
12 #include <rtthread.h>
13 #include "board.h"
14 #include "pin_mux.h"
15 #include "fsl_iomuxc.h"
16 #ifdef BSP_USING_DMA
17 #include "fsl_dmamux.h"
18 #include "fsl_edma.h"
19 #endif
20
21 #define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority
22 4 bits for subpriority */
23 #define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority
24 3 bits for subpriority */
25 #define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority
26 2 bits for subpriority */
27 #define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority
28 1 bits for subpriority */
29 #define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority
30 0 bits for subpriority */
31
32
33 /* MPU configuration. */
BOARD_ConfigMPU(void)34 void BOARD_ConfigMPU(void)
35 {
36 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
37 extern uint32_t Image$$RW_m_ncache$$Base[];
38 /* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */
39 extern uint32_t Image$$RW_m_ncache_unused$$Base[];
40 extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[];
41 uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base;
42 uint32_t size = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ?
43 0 :
44 ((uint32_t)Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart);
45 #elif defined(__MCUXPRESSO)
46 extern uint32_t __base_NCACHE_REGION;
47 extern uint32_t __top_NCACHE_REGION;
48 uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION);
49 uint32_t size = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart;
50 #elif defined(__ICCARM__) || defined(__GNUC__)
51 extern uint32_t __NCACHE_REGION_START[];
52 extern uint32_t __NCACHE_REGION_SIZE[];
53 uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START;
54 uint32_t size = (uint32_t)__NCACHE_REGION_SIZE;
55 #endif
56 volatile uint32_t i = 0;
57
58 /* Disable I cache and D cache */
59 if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
60 {
61 SCB_DisableICache();
62 }
63 if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
64 {
65 SCB_DisableDCache();
66 }
67
68 /* Disable MPU */
69 ARM_MPU_Disable();
70
71 /* MPU configure:
72 * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
73 * SubRegionDisable, Size)
74 * API in mpu_armv7.h.
75 * param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
76 * disabled.
77 * param AccessPermission Data access permissions, allows you to configure read/write access for User and
78 * Privileged mode.
79 * Use MACROS defined in mpu_armv7.h:
80 * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
81 * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
82 * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache
83 * 0 x 0 0 Strongly Ordered shareable
84 * 0 x 0 1 Device shareable
85 * 0 0 1 0 Normal not shareable Outer and inner write
86 * through no write allocate
87 * 0 0 1 1 Normal not shareable Outer and inner write
88 * back no write allocate
89 * 0 1 1 0 Normal shareable Outer and inner write
90 * through no write allocate
91 * 0 1 1 1 Normal shareable Outer and inner write
92 * back no write allocate
93 * 1 0 0 0 Normal not shareable outer and inner
94 * noncache
95 * 1 1 0 0 Normal shareable outer and inner
96 * noncache
97 * 1 0 1 1 Normal not shareable outer and inner write
98 * back write/read acllocate
99 * 1 1 1 1 Normal shareable outer and inner write
100 * back write/read acllocate
101 * 2 x 0 0 Device not shareable
102 * Above are normal use settings, if your want to see more details or want to config different inner/outter cache
103 * policy.
104 * please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
105 * param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
106 * param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
107 * mpu_armv7.h.
108 */
109
110 /*
111 * Add default region to deny access to whole address space to workaround speculative prefetch.
112 * Refer to Arm errata 1013783-B for more details.
113 *
114 */
115 /* Region 0 setting: Instruction access disabled, No data access permission. */
116 MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U);
117 MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 0, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB);
118
119 /* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
120 MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
121 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
122
123 /* Region 2 setting: Memory with Device type, not shareable, non-cacheable. */
124 MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
125 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
126
127 #if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
128 /* Region 3 setting: Memory with Normal type, not shareable, outer/inner write back. */
129 MPU->RBAR = ARM_MPU_RBAR(3, 0x60000000U);
130 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_8MB);
131 #endif
132
133 /* Region 4 setting: Memory with Device type, not shareable, non-cacheable. */
134 MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
135 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
136
137 /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
138 MPU->RBAR = ARM_MPU_RBAR(5, 0x00000000U);
139 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64KB);
140
141 /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
142 MPU->RBAR = ARM_MPU_RBAR(6, 0x20000000U);
143 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64KB);
144
145 /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
146 MPU->RBAR = ARM_MPU_RBAR(7, 0x20200000U);
147 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
148
149 /* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back */
150 MPU->RBAR = ARM_MPU_RBAR(8, 0x80000000U);
151 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
152
153 while ((size >> i) > 0x1U)
154 {
155 i++;
156 }
157
158 if (i != 0)
159 {
160 /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
161 assert(!(nonCacheStart % size));
162 assert(size == (uint32_t)(1 << i));
163 assert(i >= 5);
164
165 /* Region 9 setting: Memory with Normal type, not shareable, non-cacheable */
166 MPU->RBAR = ARM_MPU_RBAR(9, nonCacheStart);
167 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1);
168 }
169
170 /* Region 10 setting: Memory with Device type, not shareable, non-cacheable */
171 MPU->RBAR = ARM_MPU_RBAR(10, 0x40000000);
172 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4MB);
173
174 /* Enable MPU */
175 ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
176
177 /* Enable I cache and D cache */
178 SCB_EnableDCache();
179 SCB_EnableICache();
180 }
181 /* This is the timer interrupt service routine. */
SysTick_Handler(void)182 void SysTick_Handler(void)
183 {
184 /* enter interrupt */
185 rt_interrupt_enter();
186
187 rt_tick_increase();
188
189 /* leave interrupt */
190 rt_interrupt_leave();
191 }
192
193 #ifdef BSP_USING_DMA
imxrt_dma_init(void)194 void imxrt_dma_init(void)
195 {
196 edma_config_t config;
197
198 DMAMUX_Init(DMAMUX);
199 EDMA_GetDefaultConfig(&config);
200 EDMA_Init(DMA0, &config);
201 }
202 #endif
203 #ifdef BSP_USING_ETH
imxrt_enet_pins_init(void)204 void imxrt_enet_pins_init(void)
205 {
206 IOMUXC_SetPinMux(
207 IOMUXC_GPIO_AD_B0_04_GPIO1_IO04, /* GPIO_AD_B0_04 is configured as GPIO1_IO04 */
208 0U); /* Software Input On Field: Input Path is determined by functionality */
209 /* Software Input On Field: Input Path is determined by functionality */
210 IOMUXC_SetPinMux(
211 IOMUXC_GPIO_AD_B0_08_ENET_REF_CLK1, /* GPIO_AD_B0_08 is configured as ENET_REF_CLK1 */
212 1U); /* Software Input On Field: Force input path of pad GPIO_AD_B0_08 */
213 IOMUXC_SetPinMux(
214 IOMUXC_GPIO_AD_B0_09_ENET_RDATA01, /* GPIO_AD_B0_09 is configured as ENET_RDATA01 */
215 0U); /* Software Input On Field: Input Path is determined by functionality */
216 IOMUXC_SetPinMux(
217 IOMUXC_GPIO_AD_B0_10_ENET_RDATA00, /* GPIO_AD_B0_10 is configured as ENET_RDATA00 */
218 0U); /* Software Input On Field: Input Path is determined by functionality */
219 IOMUXC_SetPinMux(
220 IOMUXC_GPIO_AD_B0_11_ENET_RX_EN, /* GPIO_AD_B0_11 is configured as ENET_RX_EN */
221 0U); /* Software Input On Field: Input Path is determined by functionality */
222 IOMUXC_SetPinMux(
223 IOMUXC_GPIO_AD_B0_12_ENET_RX_ER, /* GPIO_AD_B0_12 is configured as ENET_RX_ER */
224 0U); /* Software Input On Field: Input Path is determined by functionality */
225 IOMUXC_SetPinMux(
226 IOMUXC_GPIO_AD_B0_13_ENET_TX_EN, /* GPIO_AD_B0_13 is configured as ENET_TX_EN */
227 0U); /* Software Input On Field: Input Path is determined by functionality */
228 IOMUXC_SetPinMux(
229 IOMUXC_GPIO_AD_B0_14_ENET_TDATA00, /* GPIO_AD_B0_14 is configured as ENET_TDATA00 */
230 0U); /* Software Input On Field: Input Path is determined by functionality */
231 IOMUXC_SetPinMux(
232 IOMUXC_GPIO_AD_B0_15_ENET_TDATA01, /* GPIO_AD_B0_15 is configured as ENET_TDATA01 */
233 0U); /* Software Input On Field: Input Path is determined by functionality */
234 IOMUXC_SetPinMux(
235 IOMUXC_GPIO_AD_B1_06_GPIO1_IO22, /* GPIO_AD_B1_06 is configured as GPIO1_IO22 */
236 0U); /* Software Input On Field: Input Path is determined by functionality */
237 IOMUXC_SetPinMux(
238 IOMUXC_GPIO_EMC_40_ENET_MDIO, /* GPIO_EMC_40 is configured as ENET_MDIO */
239 0U); /* Software Input On Field: Input Path is determined by functionality */
240 IOMUXC_SetPinMux(
241 IOMUXC_GPIO_EMC_41_ENET_MDC, /* GPIO_EMC_41 is configured as ENET_MDC */
242 0U); /* Software Input On Field: Input Path is determined by functionality */
243 IOMUXC_SetPinConfig(
244 IOMUXC_GPIO_AD_B0_04_GPIO1_IO04, /* GPIO_AD_B0_04 PAD functional properties : */
245 0xB0A9U); /* Slew Rate Field: Fast Slew Rate
246 Drive Strength Field: R0/5
247 Speed Field: medium(100MHz)
248 Open Drain Enable Field: Open Drain Disabled
249 Pull / Keep Enable Field: Pull/Keeper Enabled
250 Pull / Keep Select Field: Pull
251 Pull Up / Down Config. Field: 100K Ohm Pull Up
252 Hyst. Enable Field: Hysteresis Disabled */
253 IOMUXC_SetPinConfig(
254 IOMUXC_GPIO_AD_B0_08_ENET_REF_CLK1, /* GPIO_AD_B0_08 PAD functional properties : */
255 0xB0E9U); /* Slew Rate Field: Fast Slew Rate
256 Drive Strength Field: R0/5
257 Speed Field: max(200MHz)
258 Open Drain Enable Field: Open Drain Disabled
259 Pull / Keep Enable Field: Pull/Keeper Enabled
260 Pull / Keep Select Field: Pull
261 Pull Up / Down Config. Field: 100K Ohm Pull Up
262 Hyst. Enable Field: Hysteresis Disabled */
263 IOMUXC_SetPinConfig(
264 IOMUXC_GPIO_AD_B0_09_ENET_RDATA01, /* GPIO_AD_B0_09 PAD functional properties : */
265 0xB0E9U); /* Slew Rate Field: Fast Slew Rate
266 Drive Strength Field: R0/5
267 Speed Field: max(200MHz)
268 Open Drain Enable Field: Open Drain Disabled
269 Pull / Keep Enable Field: Pull/Keeper Enabled
270 Pull / Keep Select Field: Pull
271 Pull Up / Down Config. Field: 100K Ohm Pull Up
272 Hyst. Enable Field: Hysteresis Disabled */
273 IOMUXC_SetPinConfig(
274 IOMUXC_GPIO_AD_B0_10_ENET_RDATA00, /* GPIO_AD_B0_10 PAD functional properties : */
275 0xB0E9U); /* Slew Rate Field: Fast Slew Rate
276 Drive Strength Field: R0/5
277 Speed Field: max(200MHz)
278 Open Drain Enable Field: Open Drain Disabled
279 Pull / Keep Enable Field: Pull/Keeper Enabled
280 Pull / Keep Select Field: Pull
281 Pull Up / Down Config. Field: 100K Ohm Pull Up
282 Hyst. Enable Field: Hysteresis Disabled */
283 IOMUXC_SetPinConfig(
284 IOMUXC_GPIO_AD_B0_11_ENET_RX_EN, /* GPIO_AD_B0_11 PAD functional properties : */
285 0xB0E9U); /* Slew Rate Field: Fast Slew Rate
286 Drive Strength Field: R0/5
287 Speed Field: max(200MHz)
288 Open Drain Enable Field: Open Drain Disabled
289 Pull / Keep Enable Field: Pull/Keeper Enabled
290 Pull / Keep Select Field: Pull
291 Pull Up / Down Config. Field: 100K Ohm Pull Up
292 Hyst. Enable Field: Hysteresis Disabled */
293 IOMUXC_SetPinConfig(
294 IOMUXC_GPIO_AD_B0_12_ENET_RX_ER, /* GPIO_AD_B0_12 PAD functional properties : */
295 0xB0E9U); /* Slew Rate Field: Fast Slew Rate
296 Drive Strength Field: R0/5
297 Speed Field: max(200MHz)
298 Open Drain Enable Field: Open Drain Disabled
299 Pull / Keep Enable Field: Pull/Keeper Enabled
300 Pull / Keep Select Field: Pull
301 Pull Up / Down Config. Field: 100K Ohm Pull Up
302 Hyst. Enable Field: Hysteresis Disabled */
303 IOMUXC_SetPinConfig(
304 IOMUXC_GPIO_AD_B0_13_ENET_TX_EN, /* GPIO_AD_B0_13 PAD functional properties : */
305 0xB0E9U); /* Slew Rate Field: Fast Slew Rate
306 Drive Strength Field: R0/5
307 Speed Field: max(200MHz)
308 Open Drain Enable Field: Open Drain Disabled
309 Pull / Keep Enable Field: Pull/Keeper Enabled
310 Pull / Keep Select Field: Pull
311 Pull Up / Down Config. Field: 100K Ohm Pull Up
312 Hyst. Enable Field: Hysteresis Disabled */
313 IOMUXC_SetPinConfig(
314 IOMUXC_GPIO_AD_B0_14_ENET_TDATA00, /* GPIO_AD_B0_14 PAD functional properties : */
315 0xB0E9U); /* Slew Rate Field: Fast Slew Rate
316 Drive Strength Field: R0/5
317 Speed Field: max(200MHz)
318 Open Drain Enable Field: Open Drain Disabled
319 Pull / Keep Enable Field: Pull/Keeper Enabled
320 Pull / Keep Select Field: Pull
321 Pull Up / Down Config. Field: 100K Ohm Pull Up
322 Hyst. Enable Field: Hysteresis Disabled */
323 IOMUXC_SetPinConfig(
324 IOMUXC_GPIO_AD_B0_15_ENET_TDATA01, /* GPIO_AD_B0_15 PAD functional properties : */
325 0xB0E9U); /* Slew Rate Field: Fast Slew Rate
326 Drive Strength Field: R0/5
327 Speed Field: max(200MHz)
328 Open Drain Enable Field: Open Drain Disabled
329 Pull / Keep Enable Field: Pull/Keeper Enabled
330 Pull / Keep Select Field: Pull
331 Pull Up / Down Config. Field: 100K Ohm Pull Up
332 Hyst. Enable Field: Hysteresis Disabled */
333 IOMUXC_SetPinConfig(
334 IOMUXC_GPIO_AD_B1_06_GPIO1_IO22, /* GPIO_AD_B1_06 PAD functional properties : */
335 0xB0A9U); /* Slew Rate Field: Fast Slew Rate
336 Drive Strength Field: R0/5
337 Speed Field: medium(100MHz)
338 Open Drain Enable Field: Open Drain Disabled
339 Pull / Keep Enable Field: Pull/Keeper Enabled
340 Pull / Keep Select Field: Pull
341 Pull Up / Down Config. Field: 100K Ohm Pull Up
342 Hyst. Enable Field: Hysteresis Disabled */
343 IOMUXC_SetPinConfig(
344 IOMUXC_GPIO_EMC_40_ENET_MDIO, /* GPIO_EMC_40 PAD functional properties : */
345 0xB0E9U); /* Slew Rate Field: Fast Slew Rate
346 Drive Strength Field: R0/5
347 Speed Field: max(200MHz)
348 Open Drain Enable Field: Open Drain Disabled
349 Pull / Keep Enable Field: Pull/Keeper Enabled
350 Pull / Keep Select Field: Pull
351 Pull Up / Down Config. Field: 100K Ohm Pull Up
352 Hyst. Enable Field: Hysteresis Disabled */
353 IOMUXC_SetPinConfig(
354 IOMUXC_GPIO_EMC_41_ENET_MDC, /* GPIO_EMC_41 PAD functional properties : */
355 0xB0E9U); /* Slew Rate Field: Fast Slew Rate
356 Drive Strength Field: R0/5
357 Speed Field: max(200MHz)
358 Open Drain Enable Field: Open Drain Disabled
359 Pull / Keep Enable Field: Pull/Keeper Enabled
360 Pull / Keep Select Field: Pull
361 Pull Up / Down Config. Field: 100K Ohm Pull Up
362 Hyst. Enable Field: Hysteresis Disabled */
363 }
364
365 #ifndef BSP_USING_PHY
imxrt_enet_phy_reset_by_gpio(void)366 void imxrt_enet_phy_reset_by_gpio(void)
367 {
368 gpio_pin_config_t gpio_config = {kGPIO_DigitalOutput, 0, kGPIO_NoIntmode};
369
370 GPIO_PinInit(GPIO1, 9, &gpio_config);
371 GPIO_PinInit(GPIO1, 10, &gpio_config);
372 /* pull up the ENET_INT before RESET. */
373 GPIO_WritePinOutput(GPIO1, 10, 1);
374 GPIO_WritePinOutput(GPIO1, 9, 0);
375 rt_thread_delay(100);
376 GPIO_WritePinOutput(GPIO1, 9, 1);
377 }
378 #endif /* BSP_USING_PHY */
379
380 #endif /* BSP_USING_ETH */
381
382 #ifdef BSP_USING_PHY
imxrt_phy_pins_init(void)383 void imxrt_phy_pins_init( void )
384 {
385 // IOMUXC_SetPinMux(
386 // IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */
387 // 0U); /* Software Input On Field: Input Path is determined by functionality */
388 // IOMUXC_SetPinConfig(
389 // IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_B0_00 PAD functional properties : */
390 // 0x10B0u); /* Slew Rate Field: Slow Slew Rate
391 // Drive Strength Field: R0/6
392 // Speed Field: medium(100MHz)
393 // Open Drain Enable Field: Open Drain Disabled
394 // Pull / Keep Enable Field: Pull/Keeper Enabled
395 // Pull / Keep Select Field: Keeper
396 // Pull Up / Down Config. Field: 100K Ohm Pull Down
397 // Hyst. Enable Field: Hysteresis Disabled */
398
399 IOMUXC_SetPinMux(
400 IOMUXC_GPIO_AD_B0_04_GPIO1_IO04, /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */
401 0U); /* Software Input On Field: Input Path is determined by functionality */
402 IOMUXC_SetPinConfig(
403 IOMUXC_GPIO_AD_B0_04_GPIO1_IO04, /* GPIO_B0_00 PAD functional properties : */
404 0x10B0u); /* Slew Rate Field: Slow Slew Rate
405 Drive Strength Field: R0/6
406 Speed Field: medium(100MHz)
407 Open Drain Enable Field: Open Drain Disabled
408 Pull / Keep Enable Field: Pull/Keeper Enabled
409 Pull / Keep Select Field: Keeper
410 Pull Up / Down Config. Field: 100K Ohm Pull Down
411 Hyst. Enable Field: Hysteresis Disabled */
412 }
413 #endif /* BSP_USING_PHY */
414
415
416
417
418 /**
419 * This function will initial rt1050 board.
420 */
rt_hw_board_init()421 void rt_hw_board_init()
422 {
423 BOARD_ConfigMPU();
424 BOARD_InitPins();
425 BOARD_BootClockRUN();
426
427 NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
428 SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
429
430 #ifdef BSP_USING_DMA
431 imxrt_dma_init();
432 #endif
433
434 #ifdef BSP_USING_ETH
435 imxrt_enet_pins_init();
436 #endif
437
438 #ifdef BSP_USING_PHY
439 imxrt_phy_pins_init();
440 #endif
441 #ifdef RT_USING_HEAP
442 rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
443 #endif
444
445 #ifdef RT_USING_COMPONENTS_INIT
446 rt_components_board_init();
447 #endif
448
449 #ifdef RT_USING_CONSOLE
450 rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
451 #endif
452 }
453
454
455
456
457