1/*
2** ###################################################################
3**     Processors:          MIMXRT1052CVL5A
4**                          MIMXRT1052DVL6A
5**
6**     Compiler:            IAR ANSI C/C++ Compiler for ARM
7**     Reference manual:    IMXRT1050RM Rev.C, 08/2017
8**     Version:             rev. 0.1, 2017-01-10
9**     Build:               b170927
10**
11**     Abstract:
12**         Linker file for the IAR ANSI C/C++ Compiler for ARM
13**
14**     Copyright 2016 Freescale Semiconductor, Inc.
15**     Copyright 2016-2017 NXP
16**     Redistribution and use in source and binary forms, with or without modification,
17**     are permitted provided that the following conditions are met:
18**
19**     1. Redistributions of source code must retain the above copyright notice, this list
20**       of conditions and the following disclaimer.
21**
22**     2. Redistributions in binary form must reproduce the above copyright notice, this
23**       list of conditions and the following disclaimer in the documentation and/or
24**       other materials provided with the distribution.
25**
26**     3. Neither the name of the copyright holder nor the names of its
27**       contributors may be used to endorse or promote products derived from this
28**       software without specific prior written permission.
29**
30**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
31**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
32**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
33**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
34**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
35**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
36**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
37**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
39**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40**
41**     http:                 www.nxp.com
42**     mail:                 support@nxp.com
43**
44** ###################################################################
45*/
46
47define symbol m_interrupts_start       = 0x60002000;
48define symbol m_interrupts_end         = 0x600023FF;
49
50define symbol m_itcm_start             = 0x00000000;
51define symbol m_itcm_end               = 0x0001FFFF;
52
53define symbol m_spiflash_start         = 0x60002400;
54define symbol m_spiflash_end           = 0x7F7FFFFF;
55
56define symbol m_dtcm_start             = 0x20000000;
57define symbol m_dtcm_end               = 0x2001FFFF;/* DTCM 128KB */
58
59define symbol m_ocram_start            = 0x20200000;
60define symbol m_ocram_end              = 0x2020FFFF;/* OCRAM 64KB */
61
62define symbol m_sdram_start            = 0x80000000;
63define symbol m_sdram_end              = 0x81DFFFFF;
64
65define symbol m_ncache_start           = 0x81E00000;
66define symbol m_ncache_end             = 0x81FFFFFF;
67
68define exported symbol m_boot_hdr_conf_start = 0x60000000;
69define symbol m_boot_hdr_ivt_start           = 0x60001000;
70define symbol m_boot_hdr_boot_data_start     = 0x60001020;
71define symbol m_boot_hdr_dcd_data_start      = 0x60001030;
72
73/* Sizes */
74if (isdefinedsymbol(__stack_size__)) {
75  define symbol __size_cstack__        = __stack_size__;
76} else {
77  define symbol __size_cstack__        = 0x0400;
78}
79
80if (isdefinedsymbol(__heap_size__)) {
81  define symbol __size_heap__          = __heap_size__;
82} else {
83  define symbol __size_heap__          = 0x0400;
84}
85
86define exported symbol __VECTOR_TABLE  = m_interrupts_start;
87define exported symbol __VECTOR_RAM    = m_interrupts_start;
88define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0;
89define exported symbol __RTT_HEAP_END = m_dtcm_end;
90
91define memory mem with size = 4G;
92define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
93                          | mem:[from m_spiflash_start to m_spiflash_end];
94
95define region ITCM_region = mem:[from m_itcm_start to m_itcm_end];
96define region DTCM_region = mem:[from m_dtcm_start to m_dtcm_end];
97define region OCRAM_region = mem:[from m_ocram_start to m_ocram_end];
98define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end];
99define region SDRAM_region = mem:[from m_sdram_start to m_sdram_end];
100
101define block CSTACK    with alignment = 8, size = __size_cstack__   { };
102define block HEAP      with alignment = 8, size = __size_heap__     { };
103define block RW        { readwrite };
104define block ZI        { zi };
105define block NCACHE_VAR    { section NonCacheable , section NonCacheable.init };
106
107initialize by copy { readwrite, section .textrw};
108do not initialize  { section .noinit };
109
110place at address mem: m_interrupts_start    { readonly section .intvec };
111
112place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf };
113place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt };
114place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data };
115place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data };
116
117keep { section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data };
118keep { section FSymTab };
119keep { section VSymTab };
120keep { section .rti_fn* };
121
122place in TEXT_region                        { readonly };
123place in DTCM_region                        { block RW };
124place in DTCM_region                        { block ZI };
125place in DTCM_region                        { last block HEAP };
126place in DTCM_region                        { block CSTACK };
127place in NCACHE_region                      { block NCACHE_VAR };
128