1#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m7 -E -x c
2/*
3** ###################################################################
4**     Processors:          MIMXRT1021CAF4A
5**                          MIMXRT1021CAG4A
6**                          MIMXRT1021DAF5A
7**                          MIMXRT1021DAG5A
8**
9**     Compiler:            Keil ARM C/C++ Compiler
10**     Reference manual:    IMXRT1020RM Rev.1, 12/2018 | IMXRT1020SRM Rev.3
11**     Version:             rev. 0.1, 2017-06-06
12**     Build:               b210709
13**
14**     Abstract:
15**         Linker file for the Keil ARM C/C++ Compiler
16**
17**     Copyright 2016 Freescale Semiconductor, Inc.
18**     Copyright 2016-2021 NXP
19**     All rights reserved.
20**
21**     SPDX-License-Identifier: BSD-3-Clause
22**
23**     http:                 www.nxp.com
24**     mail:                 support@nxp.com
25**
26** ###################################################################
27*/
28
29#if (defined(__ram_vector_table__))
30  #define __ram_vector_table_size__    0x00000400
31#else
32  #define __ram_vector_table_size__    0x00000000
33#endif
34
35#define m_flash_config_start           0x60000000
36#define m_flash_config_size            0x00001000
37
38#define m_ivt_start                    0x60001000
39#define m_ivt_size                     0x00001000
40
41#define m_interrupts_start             0x60002000
42#define m_interrupts_size              0x00000400
43
44#define m_text_start                   0x60002400
45#define m_text_size                    0x007FDC00
46
47#define m_qacode_start                 0x00000000
48#define m_qacode_size                  0x00010000
49
50#define m_interrupts_ram_start         0x20000000
51#define m_interrupts_ram_size          __ram_vector_table_size__
52
53#define m_data_start                   (m_interrupts_ram_start + m_interrupts_ram_size)
54#define m_data_size                    (0x00010000 - m_interrupts_ram_size)
55
56#define m_data2_start                  0x20200000
57#define m_data2_size                   0x00020000
58
59/* Sizes */
60#if (defined(__stack_size__))
61  #define Stack_Size                   __stack_size__
62#else
63  #define Stack_Size                   0x2000
64#endif
65
66#if (defined(__heap_size__))
67  #define Heap_Size                    __heap_size__
68#else
69  #define Heap_Size                    0x6000
70#endif
71
72#define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK))
73
74#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
75LR_m_text m_flash_config_start m_text_start+m_text_size-m_flash_config_start {   ; load region size_region
76  RW_m_config_text m_flash_config_start FIXED m_flash_config_size { ; load address = execution address
77    * (.boot_hdr.conf, +FIRST)
78  }
79
80  RW_m_ivt_text m_ivt_start FIXED m_ivt_size { ; load address = execution address
81    * (.boot_hdr.ivt, +FIRST)
82    * (.boot_hdr.boot_data)
83    * (.boot_hdr.dcd_data)
84  }
85#else
86LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start {   ; load region size_region
87#endif
88  VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
89    * (.isr_vector,+FIRST)
90  }
91  ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
92    * (InRoot$$Sections)
93    .ANY (+RO)
94  }
95#if (defined(__ram_vector_table__))
96  VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size {
97  }
98#else
99  VECTOR_RAM m_interrupts_start EMPTY 0 {
100  }
101#endif
102  RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
103    .ANY (+RW +ZI)
104    * (RamFunction)
105    * (NonCacheable.init)
106    * (*NonCacheable)
107    * (DataQuickAccess)
108  }
109  ARM_LIB_HEAP +0 EMPTY Heap_Size {}
110  ARM_LIB_STACK +0 EMPTY Stack_Size{} ; Stack region growing down
111  RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{}
112
113  RW_m_ram_text m_qacode_start m_qacode_size { ;
114    * (CodeQuickAccess)
115  }
116  RW_m_ncache m_data2_start EMPTY 0 {
117  }
118  RW_m_ncache_unused +0 EMPTY m_data2_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration
119  }
120}
121
122