1 /* 2 * The Clear BSD License 3 * Copyright (c) 2016, Freescale Semiconductor, Inc. 4 * Copyright 2016-2017 NXP 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, 9 * are permitted (subject to the limitations in the disclaimer below) provided 10 * that the following conditions are met: 11 * 12 * o Redistributions of source code must retain the above copyright notice, this 13 * list 14 * of conditions and the following disclaimer. 15 * 16 * o Redistributions in binary form must reproduce the above copyright notice, 17 * this 18 * list of conditions and the following disclaimer in the documentation and/or 19 * other materials provided with the distribution. 20 * 21 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its 22 * contributors may be used to endorse or promote products derived from this 23 * software without specific prior written permission. 24 * 25 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 27 * AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 29 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 30 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 31 * FOR 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES 34 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 35 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 36 * ON 37 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 39 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 */ 41 42 #ifndef __FLEXSPI_NOR_FLASH_H__ 43 #define __FLEXSPI_NOR_FLASH_H__ 44 45 #include <stdint.h> 46 #include <stdbool.h> 47 #include "fsl_common.h" 48 49 /* FLEXSPI memory config block related defintions */ 50 #define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian 51 #define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 52 #define FLEXSPI_CFG_BLK_SIZE (512) 53 54 /* FLEXSPI Feature related definitions */ 55 #define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 56 57 /* Lookup table related defintions */ 58 #define CMD_INDEX_READ 0 59 #define CMD_INDEX_READSTATUS 1 60 #define CMD_INDEX_WRITEENABLE 2 61 #define CMD_INDEX_WRITE 4 62 63 #define CMD_LUT_SEQ_IDX_READ 0 64 #define CMD_LUT_SEQ_IDX_READSTATUS 1 65 #define CMD_LUT_SEQ_IDX_WRITEENABLE 3 66 #define CMD_LUT_SEQ_IDX_WRITE 9 67 68 #define CMD_SDR 0x01 69 #define CMD_DDR 0x21 70 #define RADDR_SDR 0x02 71 #define RADDR_DDR 0x22 72 #define CADDR_SDR 0x03 73 #define CADDR_DDR 0x23 74 #define MODE1_SDR 0x04 75 #define MODE1_DDR 0x24 76 #define MODE2_SDR 0x05 77 #define MODE2_DDR 0x25 78 #define MODE4_SDR 0x06 79 #define MODE4_DDR 0x26 80 #define MODE8_SDR 0x07 81 #define MODE8_DDR 0x27 82 #define WRITE_SDR 0x08 83 #define WRITE_DDR 0x28 84 #define READ_SDR 0x09 85 #define READ_DDR 0x29 86 #define LEARN_SDR 0x0A 87 #define LEARN_DDR 0x2A 88 #define DATSZ_SDR 0x0B 89 #define DATSZ_DDR 0x2B 90 #define DUMMY_SDR 0x0C 91 #define DUMMY_DDR 0x2C 92 #define DUMMY_RWDS_SDR 0x0D 93 #define DUMMY_RWDS_DDR 0x2D 94 #define JMP_ON_CS 0x1F 95 #define STOP 0 96 97 #define FLEXSPI_1PAD 0 98 #define FLEXSPI_2PAD 1 99 #define FLEXSPI_4PAD 2 100 #define FLEXSPI_8PAD 3 101 102 #define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ 103 (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ 104 FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) 105 106 //!@brief Definitions for FlexSPI Serial Clock Frequency 107 typedef enum _FlexSpiSerialClockFreq 108 { 109 kFlexSpiSerialClk_30MHz = 1, 110 kFlexSpiSerialClk_50MHz = 2, 111 kFlexSpiSerialClk_60MHz = 3, 112 kFlexSpiSerialClk_75MHz = 4, 113 kFlexSpiSerialClk_80MHz = 5, 114 kFlexSpiSerialClk_100MHz = 6, 115 kFlexSpiSerialClk_133MHz = 7, 116 kFlexSpiSerialClk_166MHz = 8, 117 kFlexSpiSerialClk_200MHz = 9, 118 } flexspi_serial_clk_freq_t; 119 120 //!@brief FlexSPI clock configuration type 121 enum 122 { 123 kFlexSpiClk_SDR, //!< Clock configure for SDR mode 124 kFlexSpiClk_DDR, //!< Clock configurat for DDR mode 125 }; 126 127 //!@brief FlexSPI Read Sample Clock Source definition 128 typedef enum _FlashReadSampleClkSource 129 { 130 kFlexSPIReadSampleClk_LoopbackInternally = 0, 131 kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, 132 kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, 133 kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, 134 } flexspi_read_sample_clk_t; 135 136 137 //!@brief Misc feature bit definitions 138 enum 139 { 140 kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable 141 kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable 142 kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable 143 kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable 144 kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable 145 kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable 146 kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. 147 }; 148 149 //!@brief Flash Type Definition 150 enum 151 { 152 kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR 153 kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND 154 kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH 155 kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND 156 kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs 157 }; 158 159 //!@brief Flash Pad Definitions 160 enum 161 { 162 kSerialFlash_1Pad = 1, 163 kSerialFlash_2Pads = 2, 164 kSerialFlash_4Pads = 4, 165 kSerialFlash_8Pads = 8, 166 }; 167 168 //!@brief FlexSPI LUT Sequence structure 169 typedef struct _lut_sequence 170 { 171 uint8_t seqNum; //!< Sequence Number, valid number: 1-16 172 uint8_t seqId; //!< Sequence Index, valid number: 0-15 173 uint16_t reserved; 174 } flexspi_lut_seq_t; 175 176 //!@brief Flash Configuration Command Type 177 enum 178 { 179 kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc 180 kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command 181 kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode 182 kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode 183 kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode 184 kDeviceConfigCmdType_Reset, //!< Reset device command 185 }; 186 187 //!@brief FlexSPI Memory Configuration Block 188 typedef struct _FlexSPIConfig 189 { 190 uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL 191 uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix 192 uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use 193 uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 194 uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 195 uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 196 uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For 197 //! Serial NAND, need to refer to datasheet 198 uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable 199 uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, 200 //! Generic configuration, etc. 201 uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for 202 //! DPI/QPI/OPI switch or reset command 203 flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt 204 //! sequence number, [31:16] Reserved 205 uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration 206 uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable 207 uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe 208 flexspi_lut_seq_t 209 configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq 210 uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use 211 uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands 212 uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use 213 uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more 214 //! details 215 uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details 216 uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal 217 uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot 218 //! Chapter for more details 219 uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot 220 //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH 221 uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use 222 uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 223 uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 224 uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 225 uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 226 uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value 227 uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value 228 uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value 229 uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value 230 uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command 231 uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands 232 uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns 233 uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 234 uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - 235 //! busy flag is 0 when flash device is busy 236 uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences 237 flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences 238 uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use 239 } flexspi_mem_config_t; 240 241 /* */ 242 #define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 243 #define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 244 #define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 245 #define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 246 #define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 247 #define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 248 #define NOR_CMD_INDEX_DUMMY 6 //!< 6 249 #define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 250 251 #define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block 252 #define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ 253 CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block 254 #define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ 255 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block 256 #define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ 257 CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block 258 #define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ 259 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block 260 #define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block 261 #define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block 262 #define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ 263 CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block 264 #define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block 265 #define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block 266 #define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ 267 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block 268 #define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ 269 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk 270 271 272 /* 273 * Serial NOR configuration block 274 */ 275 typedef struct _flexspi_nor_config 276 { 277 flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI 278 uint32_t pageSize; //!< Page size of Serial NOR 279 uint32_t sectorSize; //!< Sector size of Serial NOR 280 uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command 281 uint8_t isUniformBlockSize; //!< Sector/Block size is the same 282 uint8_t reserved0[2]; //!< Reserved for future use 283 uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 284 uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command 285 uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false 286 uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution 287 uint32_t blockSize; //!< Block size 288 uint32_t reserve2[11]; //!< Reserved for future use 289 } flexspi_nor_config_t; 290 291 #ifdef __cplusplus 292 extern "C" { 293 #endif 294 295 #ifdef __cplusplus 296 } 297 #endif 298 299 #endif // __FLEXSPI_NOR_FLASH_H__ 300