1#! armcc -E
2/*
3** ###################################################################
4**     Processors:          MIMXRT1052CVJ5B
5**                          MIMXRT1052CVL5B
6**                          MIMXRT1052DVJ6B
7**                          MIMXRT1052DVL6B
8**
9**     Compiler:            Keil ARM C/C++ Compiler
10**     Reference manual:    IMXRT1050RM Rev.1, 03/2018
11**     Version:             rev. 1.0, 2018-09-21
12**     Build:               b180921
13**
14**     Abstract:
15**         Linker file for the Keil ARM C/C++ Compiler
16**
17**     Copyright 2016 Freescale Semiconductor, Inc.
18**     Copyright 2016-2018 NXP
19**     All rights reserved.
20**
21**     SPDX-License-Identifier: BSD-3-Clause
22**
23**     http:                 www.nxp.com
24**     mail:                 support@nxp.com
25**
26** ###################################################################
27*/
28
29#define m_flash_config_start           0x60000000
30#define m_flash_config_size            0x00001000
31
32#define m_ivt_start                    0x60001000
33#define m_ivt_size                     0x00001000
34
35#define m_interrupts_start             0x60002000
36#define m_interrupts_size              0x00000400
37
38#define m_text_start                   0x60002400
39#define m_text_size                    0x01FFDC00
40
41#define m_data_start                   0x20000000
42#define m_data_size                    0x00020000
43
44#define m_data2_start                  0x20200000
45#define m_data2_size                   0x00040000
46
47/* Sizes */
48#if (defined(__stack_size__))
49  #define Stack_Size                   __stack_size__
50#else
51  #define Stack_Size                   0x0400
52#endif
53
54#if (defined(__heap_size__))
55  #define Heap_Size                    __heap_size__
56#else
57  #define Heap_Size                    0x0400
58#endif
59
60#define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK))
61
62#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
63LR_m_text m_flash_config_start m_text_start+m_text_size-m_flash_config_start {   ; load region size_region
64  RW_m_config_text m_flash_config_start FIXED m_flash_config_size { ; load address = execution address
65    * (.boot_hdr.conf, +FIRST)
66  }
67
68  RW_m_ivt_text m_ivt_start FIXED m_ivt_size { ; load address = execution address
69    * (.boot_hdr.ivt, +FIRST)
70    * (.boot_hdr.boot_data)
71    * (.boot_hdr.dcd_data)
72  }
73#else
74LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start {   ; load region size_region
75#endif
76  VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
77    * (RESET,+FIRST)
78  }
79  ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
80    * (InRoot$$Sections)
81    .ANY (+RO)
82  }
83  RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
84    .ANY (+RW +ZI)
85    * (NonCacheable.init)
86    * (NonCacheable)
87  }
88  ARM_LIB_HEAP +0 EMPTY Heap_Size {    ; Heap region growing up
89  }
90  ARM_LIB_STACK +0 EMPTY Stack_Size{} ; Stack region growing down
91  RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{}
92}
93