1/*
2** ###################################################################
3**     Processors:          MIMXRT1052CVJ5B
4**                          MIMXRT1052CVL5B
5**                          MIMXRT1052DVJ6B
6**                          MIMXRT1052DVL6B
7**
8**     Compiler:            IAR ANSI C/C++ Compiler for ARM
9**     Reference manual:    IMXRT1050RM Rev.1, 03/2018
10**     Version:             rev. 1.0, 2018-09-21
11**     Build:               b180921
12**
13**     Abstract:
14**         Linker file for the IAR ANSI C/C++ Compiler for ARM
15**
16**     Copyright 2016 Freescale Semiconductor, Inc.
17**     Copyright 2016-2018 NXP
18**     All rights reserved.
19**
20**     SPDX-License-Identifier: BSD-3-Clause
21**
22**     http:                 www.nxp.com
23**     mail:                 support@nxp.com
24**
25** ###################################################################
26*/
27
28define symbol m_interrupts_start       = 0x60002000;
29define symbol m_interrupts_end         = 0x600023FF;
30
31define symbol m_text_start             = 0x60002400;
32define symbol m_text_end               = 0x63FFFFFF;
33
34define symbol m_data_start             = 0x20000000;
35define symbol m_data_end               = 0x2001FFFF;
36
37define symbol m_data2_start            = 0x20200000;
38define symbol m_data2_end              = 0x2023FFFF;
39
40define exported symbol m_boot_hdr_conf_start = 0x60000000;
41define symbol m_boot_hdr_ivt_start           = 0x60001000;
42define symbol m_boot_hdr_boot_data_start     = 0x60001020;
43define symbol m_boot_hdr_dcd_data_start      = 0x60001030;
44
45/* Sizes */
46if (isdefinedsymbol(__stack_size__)) {
47  define symbol __size_cstack__        = __stack_size__;
48} else {
49  define symbol __size_cstack__        = 0x0400;
50}
51
52if (isdefinedsymbol(__heap_size__)) {
53  define symbol __size_heap__          = __heap_size__;
54} else {
55  define symbol __size_heap__          = 0x0400;
56}
57
58define exported symbol __VECTOR_TABLE  = m_interrupts_start;
59define exported symbol __VECTOR_RAM    = m_interrupts_start;
60define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0;
61define exported symbol __RTT_HEAP_END = m_data2_end;
62
63define memory mem with size = 4G;
64define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
65                          | mem:[from m_text_start to m_text_end];
66
67define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
68define region DATA2_region = mem:[from m_data2_start to m_data2_end];
69define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
70
71define block CSTACK    with alignment = 8, size = __size_cstack__   { };
72define block HEAP      with alignment = 8, size = __size_heap__     { };
73define block RW        { readwrite };
74define block ZI        { zi };
75define block NCACHE_VAR    { section NonCacheable , section NonCacheable.init };
76
77initialize by copy { readwrite, section .textrw };
78do not initialize  { section .noinit };
79
80place at address mem: m_interrupts_start    { readonly section .intvec };
81
82place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf };
83place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt };
84place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data };
85place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data };
86
87keep{ section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data };
88
89place in TEXT_region                        { readonly };
90place in DATA_region                        { block RW };
91place in DATA_region                        { block ZI };
92place in DATA_region                        { last block HEAP };
93place in DATA_region                        { block NCACHE_VAR };
94place in CSTACK_region                      { block CSTACK };
95
96