1#! armcc -E
2/*
3** ###################################################################
4**     Processors:          MIMXRT1052CVL5A
5**                          MIMXRT1052DVL6A
6**
7**     Compiler:            Keil ARM C/C++ Compiler
8**     Reference manual:    IMXRT1050RM Rev.C, 08/2017
9**     Version:             rev. 0.1, 2017-01-10
10**     Build:               b170927
11**
12**     Abstract:
13**         Linker file for the Keil ARM C/C++ Compiler
14**
15**     Copyright 2016 Freescale Semiconductor, Inc.
16**     Copyright 2016-2017 NXP
17**     Redistribution and use in source and binary forms, with or without modification,
18**     are permitted provided that the following conditions are met:
19**
20**     1. Redistributions of source code must retain the above copyright notice, this list
21**       of conditions and the following disclaimer.
22**
23**     2. Redistributions in binary form must reproduce the above copyright notice, this
24**       list of conditions and the following disclaimer in the documentation and/or
25**       other materials provided with the distribution.
26**
27**     3. Neither the name of the copyright holder nor the names of its
28**       contributors may be used to endorse or promote products derived from this
29**       software without specific prior written permission.
30**
31**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
32**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
33**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
34**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
35**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
36**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
37**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
38**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
40**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41**
42**     http:                 www.nxp.com
43**     mail:                 support@nxp.com
44**
45** ###################################################################
46*/
47
48#define m_flash_config_start           0x60000000
49#define m_flash_config_size            0x00001000
50
51#define m_ivt_start                    0x60001000
52#define m_ivt_size                     0x00001000
53
54#define m_text_start                   0x60002000
55#define m_text_size                    0x1F7FE000
56
57#define m_data_start                   0x20000000
58#define m_data_size                    0x00020000
59
60#define m_ncache_start                 0x81E00000
61#define m_ncache_size                  0x00200000
62
63/* Sizes */
64#if (defined(__stack_size__))
65  #define Stack_Size                   __stack_size__
66#else
67  #define Stack_Size                   0x1000
68#endif
69
70#if (defined(__heap_size__))
71  #define Heap_Size                    __heap_size__
72#else
73  #define Heap_Size                    0x0400
74#endif
75
76#include "../../rtconfig.h"
77
78#if (defined(BSP_USING_HYPERFLASH))
79LR_m_rom_config m_flash_config_start m_flash_config_size      ; load region size_region
80{
81    RW_m_config_text m_flash_config_start m_flash_config_size ; load address = execution address
82    {
83        * (.boot_hdr.conf, +FIRST)
84    }
85}
86
87LR_m_rom_ivt m_ivt_start m_ivt_size ; load region size_region
88{
89    RW_m_ivt_text m_ivt_start m_ivt_size ; load address = execution address
90    {
91        * (.boot_hdr.ivt, +FIRST)
92        * (.boot_hdr.boot_data)
93        * (.boot_hdr.dcd_data)
94    }
95}
96#endif
97
98#define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK))
99
100; load region size_region
101LR_IROM1 m_text_start m_text_size
102{
103    ER_IROM1 m_text_start m_text_size ; load address = execution address
104    {
105        * (RESET,+FIRST)
106        * (InRoot$$Sections)
107        .ANY (+RO)
108    }
109
110    RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size ; RW data
111    {
112        .ANY (+RW +ZI)
113    }
114
115    ARM_LIB_HEAP +0 EMPTY Heap_Size{}   ; Heap region growing up
116    ARM_LIB_STACK +0 EMPTY Stack_Size{} ; Stack region growing down
117    RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{}
118
119    ; ncache RW data
120    RW_m_ncache m_ncache_start m_ncache_size
121    {
122        * (NonCacheable.init)
123        * (NonCacheable)
124    }
125  ITCM 0x400 0xFBFF {
126        ;drv_flexspi_hyper.o(+RO)
127        ;fsl_flexspi.o(+RO)
128        * (*CLOCK_DisableClock)
129        * (*CLOCK_ControlGate)
130        * (*CLOCK_EnableClock)
131        * (*CLOCK_SetDiv)
132        * (itcm)
133    }
134}
135