1 /* 2 * Copyright (c) 2006-2018, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2018-12-05 zylx The first version for STM32F4xx 9 * 2019-4-25 misonyo port to IMXRT 10 */ 11 12 #ifndef SDRAM_PORT_H__ 13 #define SDRAM_PORT_H__ 14 15 /* parameters for sdram peripheral */ 16 17 #define SDRAM_BANK_ADDR ((uint32_t)0x80000000U) 18 /* region#0/1/2/3: kSEMC_SDRAM_CS0/1/2/3 */ 19 #define SDRAM_REGION kSEMC_SDRAM_CS0 20 /* CS pin: kSEMC_MUXCSX0/1/2/3 */ 21 #define SDRAM_CS_PIN kSEMC_MUXCSX0 22 /* size(kbyte):32MB = 32*1024*1KBytes */ 23 #define SDRAM_SIZE ((uint32_t)0x8000) 24 /* data width: kSEMC_PortSize8Bit,kSEMC_PortSize16Bit */ 25 #define SDRAM_DATA_WIDTH kSEMC_PortSize16Bit 26 /* column bit numbers: kSEMC_SdramColunm_9/10/11/12bit */ 27 #define SDRAM_COLUMN_BITS kSEMC_SdramColunm_9bit 28 /* cas latency clock number: kSEMC_LatencyOne/Two/Three */ 29 #define SDRAM_CAS_LATENCY kSEMC_LatencyThree 30 31 /* Timing configuration for W9825G6KH */ 32 /* TRP:precharge to active command time (ns) */ 33 #define SDRAM_TRP 18 34 /* TRCD:active to read/write command delay time (ns) */ 35 #define SDRAM_TRCD 18 36 /* The time between two refresh commands,Use the maximum of the (Trfc , Txsr).(ns) */ 37 #define SDRAM_REFRESH_RECOVERY 67 38 /* TWR:write recovery time (ns). */ 39 #define SDRAM_TWR 12 40 /* TRAS:active to precharge command time (ns). */ 41 #define SDRAM_TRAS 42 42 /* TRC time (ns). */ 43 #define SDRAM_TRC 60 44 /* active to active time (ns). */ 45 #define SDRAM_ACT2ACT 60 46 /* refresh time (ns). 64ms */ 47 #define SDRAM_REFRESH_ROW 64 * 1000000 / 8192 48 49 #endif /* SDRAM_PORT_H__ */ 50