1 /*
2 * Copyright (c) 2006-2018, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2009-01-05 Bernard first implementation
9 */
10
11 #include <rthw.h>
12 #include <rtthread.h>
13 #include "board.h"
14 #include "pin_mux.h"
15
16 #ifdef BSP_USING_DMA
17 #include "fsl_dmamux.h"
18 #include "fsl_edma.h"
19 #endif
20
21 #define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority
22 4 bits for subpriority */
23 #define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority
24 3 bits for subpriority */
25 #define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority
26 2 bits for subpriority */
27 #define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority
28 1 bits for subpriority */
29 #define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority
30 0 bits for subpriority */
31
32 /* MPU configuration. */
BOARD_ConfigMPU(void)33 static void BOARD_ConfigMPU(void)
34 {
35 /* Disable I cache and D cache */
36 SCB_DisableICache();
37 SCB_DisableDCache();
38
39 /* Disable MPU */
40 ARM_MPU_Disable();
41
42 /* Region 0 setting */
43 MPU->RBAR = ARM_MPU_RBAR(0, 0xC0000000U);
44 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
45
46 /* Region 1 setting */
47 MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
48 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
49
50 /* Region 2 setting */
51 // spi flash: normal type, cacheable, no bufferable, no shareable
52 MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
53 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_512MB);
54
55 /* Region 3 setting */
56 MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U);
57 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
58
59 /* Region 4 setting */
60 MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
61 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
62
63 /* Region 5 setting */
64 MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U);
65 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
66
67 /* Region 6 setting */
68 MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
69 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
70
71 #if defined(BSP_USING_SDRAM)
72 /* Region 7 setting */
73 MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U);
74 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
75
76 /* Region 8 setting */
77 MPU->RBAR = ARM_MPU_RBAR(8, 0x81E00000U);
78 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 1, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB);
79 #endif
80
81 /* Enable MPU */
82 ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
83
84 /* Enable I cache and D cache */
85 SCB_EnableDCache();
86 SCB_EnableICache();
87 }
88
89
90 /* This is the timer interrupt service routine. */
SysTick_Handler(void)91 void SysTick_Handler(void)
92 {
93 /* enter interrupt */
94 rt_interrupt_enter();
95
96 rt_tick_increase();
97
98 /* leave interrupt */
99 rt_interrupt_leave();
100 }
101
102 #ifdef BSP_USING_DMA
imxrt_dma_init(void)103 void imxrt_dma_init(void)
104 {
105 edma_config_t config;
106
107 DMAMUX_Init(DMAMUX);
108 EDMA_GetDefaultConfig(&config);
109 EDMA_Init(DMA0, &config);
110 }
111 #endif
112
rt_hw_board_init()113 void rt_hw_board_init()
114 {
115 BOARD_ConfigMPU();
116 BOARD_InitPins();
117 BOARD_BootClockRUN();
118
119 NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
120 SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
121
122 #ifdef BSP_USING_DMA
123 imxrt_dma_init();
124 #endif
125
126 #ifdef RT_USING_HEAP
127 rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
128 #endif
129
130 #ifdef RT_USING_COMPONENTS_INIT
131 rt_components_board_init();
132 #endif
133
134 #if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
135 rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
136 #endif
137 }
138
139