1 /*
2  * Copyright 2018 NXP
3  * All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 /*
9  * How to setup clock using clock driver functions:
10  *
11  * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
12  *
13  * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
14  *
15  * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
16  *
17  * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
18  *
19  * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
20  *
21  */
22 
23 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
24 !!GlobalInfo
25 product: Clocks v4.1
26 processor: MIMXRT1064xxxxA
27 package_id: MIMXRT1064DVL6A
28 mcu_data: ksdk2_0
29 processor_version: 0.0.0
30 board: MIMXRT1064-EVK
31  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
32 
33 #include "clock_config.h"
34 
35 /*******************************************************************************
36  * Definitions
37  ******************************************************************************/
38 
39 /*******************************************************************************
40  * Variables
41  ******************************************************************************/
42 /* System clock frequency. */
43 extern uint32_t SystemCoreClock;
44 
45 /*******************************************************************************
46  ************************ BOARD_InitBootClocks function ************************
47  ******************************************************************************/
BOARD_InitBootClocks(void)48 void BOARD_InitBootClocks(void)
49 {
50     BOARD_BootClockRUN();
51 }
52 
53 /*******************************************************************************
54  ********************** Configuration BOARD_BootClockRUN ***********************
55  ******************************************************************************/
56 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
57 !!Configuration
58 name: BOARD_BootClockRUN
59 called_from_default_init: true
60 outputs:
61 - {id: AHB_CLK_ROOT.outFreq, value: 600 MHz}
62 - {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
63 - {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
64 - {id: CLK_1M.outFreq, value: 1 MHz}
65 - {id: CLK_24M.outFreq, value: 24 MHz}
66 - {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
67 - {id: ENET2_125M_CLK.outFreq, value: 1.2 MHz}
68 - {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
69 - {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
70 - {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
71 - {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
72 - {id: FLEXSPI2_CLK_ROOT.outFreq, value: 2880/11 MHz}
73 - {id: FLEXSPI_CLK_ROOT.outFreq, value: 2880/11 MHz}
74 - {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
75 - {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
76 - {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
77 - {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
78 - {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
79 - {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
80 - {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz}
81 - {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
82 - {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
83 - {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
84 - {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
85 - {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
86 - {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz}
87 - {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
88 - {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
89 - {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
90 settings:
91 - {id: CCM.AHB_PODF.scale, value: '1', locked: true}
92 - {id: CCM.ARM_PODF.scale, value: '2', locked: true}
93 - {id: CCM.FLEXSPI2_PODF.scale, value: '1', locked: true}
94 - {id: CCM.FLEXSPI2_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
95 - {id: CCM.FLEXSPI_PODF.scale, value: '1', locked: true}
96 - {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
97 - {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
98 - {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
99 - {id: CCM.SEMC_PODF.scale, value: '8'}
100 - {id: CCM.TRACE_PODF.scale, value: '3', locked: true}
101 - {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
102 - {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
103 - {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
104 - {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
105 - {id: CCM_ANALOG.PLL2.div, value: '22'}
106 - {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
107 - {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
108 - {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
109 - {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
110 - {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
111 - {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
112 - {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
113 - {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
114 - {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true}
115 - {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
116 - {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
117 - {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
118 - {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
119 - {id: CCM_ANALOG.PLL4.denom, value: '50'}
120 - {id: CCM_ANALOG.PLL4.div, value: '47'}
121 - {id: CCM_ANALOG.PLL5.denom, value: '1'}
122 - {id: CCM_ANALOG.PLL5.div, value: '40'}
123 - {id: CCM_ANALOG.PLL5.num, value: '0'}
124 - {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
125 - {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
126 sources:
127 - {id: XTALOSC24M.OSC.outFreq, value: 24 MHz, enabled: true}
128 - {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
129  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
130 
131 /*******************************************************************************
132  * Variables for BOARD_BootClockRUN configuration
133  ******************************************************************************/
134 const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
135     {
136         .loopDivider = 100,                       /* PLL loop divider, Fout = Fin * 50 */
137         .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
138     };
139 const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
140     {
141         .loopDivider = 1,                         /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
142         .numerator = 0,                           /* 30 bit numerator of fractional loop divider */
143         .denominator = 1,                         /* 30 bit denominator of fractional loop divider */
144         .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
145     };
146 const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
147     {
148         .loopDivider = 0,                         /* PLL loop divider, Fout = Fin * 20 */
149         .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
150     };
151 /*******************************************************************************
152  * Code for BOARD_BootClockRUN configuration
153  ******************************************************************************/
BOARD_BootClockRUN(void)154 void BOARD_BootClockRUN(void)
155 {
156     /* Init RTC OSC clock frequency. */
157     CLOCK_SetRtcXtalFreq(32768U);
158     /* Enable 1MHz clock output. */
159     XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
160     /* Use free 1MHz clock output. */
161     XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
162     /* Set XTAL 24MHz clock frequency. */
163     CLOCK_SetXtalFreq(24000000U);
164     /* Enable XTAL 24MHz clock source. */
165     CLOCK_InitExternalClk(0);
166     /* Enable internal RC. */
167     CLOCK_InitRcOsc24M();
168     /* Switch clock source to external OSC. */
169     CLOCK_SwitchOsc(kCLOCK_XtalOsc);
170     /* Set Oscillator ready counter value. */
171     CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
172     /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
173     CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
174     CLOCK_SetMux(kCLOCK_PeriphMux, 1);     /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
175     /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */
176     DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13);
177     /* Waiting for DCDC_STS_DC_OK bit is asserted */
178     while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
179     {
180     }
181     /* Init ARM PLL. */
182     CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
183     /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
184      * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
185      * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
186 #ifndef SKIP_SYSCLK_INIT
187     /* Init System PLL. */
188     CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
189     /* Init System pfd0. */
190     CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
191     /* Init System pfd1. */
192     CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
193     /* Init System pfd2. */
194     CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
195     /* Init System pfd3. */
196     CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
197 #endif
198     /* In SDK projects, external flash (configured by FLEXSPI2) will be initialized by dcd.
199      * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI2 clock source in SDK projects) will be left unchanged.
200      * Note: If another clock source is selected for FLEXSPI2, user may want to avoid changing that clock as well.*/
201 #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
202     /* Init Usb1 PLL. */
203     CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
204     /* Init Usb1 pfd0. */
205     CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
206     /* Init Usb1 pfd1. */
207     CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
208     /* Init Usb1 pfd2. */
209     CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
210     /* Init Usb1 pfd3. */
211     CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
212     /* Disable Usb1 PLL output for USBPHY1. */
213     CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
214 #endif
215     /* DeInit Audio PLL. */
216     CLOCK_DeinitAudioPll();
217     /* Bypass Audio PLL. */
218     CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
219     /* Set divider for Audio PLL. */
220     CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
221     CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
222     /* Enable Audio PLL output. */
223     CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
224     /* DeInit Video PLL. */
225     CLOCK_DeinitVideoPll();
226     /* Bypass Video PLL. */
227     CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK;
228     /* Set divider for Video PLL. */
229     CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0);
230     /* Enable Video PLL output. */
231     CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
232     /* DeInit Enet PLL. */
233     CLOCK_DeinitEnetPll();
234     /* Bypass Enet PLL. */
235     CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
236     /* Set Enet output divider. */
237     CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
238     /* Enable Enet output. */
239     CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
240     /* Set Enet2 output divider. */
241     CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0);
242     /* Enable Enet2 output. */
243     CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK;
244     /* Enable Enet25M output. */
245     CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
246     /* DeInit Usb2 PLL. */
247     CLOCK_DeinitUsb2Pll();
248     /* Bypass Usb2 PLL. */
249     CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1);
250     /* Enable Usb2 PLL output. */
251     CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK;
252     /* Set AHB_PODF. */
253     CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
254     /* Disable IPG clock gate. */
255     CLOCK_DisableClock(kCLOCK_Adc1);
256     CLOCK_DisableClock(kCLOCK_Adc2);
257     CLOCK_DisableClock(kCLOCK_Xbar1);
258     CLOCK_DisableClock(kCLOCK_Xbar2);
259     /* Set IPG_PODF. */
260     CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
261     /* Set ARM_PODF. */
262     CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
263     /* Set preperiph clock source. */
264     CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
265     /* Set periph clock source. */
266     CLOCK_SetMux(kCLOCK_PeriphMux, 0);
267     /* Set PERIPH_CLK2_PODF. */
268     CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
269     /* Set periph clock2 clock source. */
270     CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
271     /* Disable PERCLK clock gate. */
272     CLOCK_DisableClock(kCLOCK_Gpt1);
273     CLOCK_DisableClock(kCLOCK_Gpt1S);
274     CLOCK_DisableClock(kCLOCK_Gpt2);
275     CLOCK_DisableClock(kCLOCK_Gpt2S);
276     CLOCK_DisableClock(kCLOCK_Pit);
277     /* Set PERCLK_PODF. */
278     CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
279     /* Set per clock source. */
280     CLOCK_SetMux(kCLOCK_PerclkMux, 0);
281     /* Disable USDHC1 clock gate. */
282     CLOCK_DisableClock(kCLOCK_Usdhc1);
283     /* Set USDHC1_PODF. */
284     CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
285     /* Set Usdhc1 clock source. */
286     CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
287     /* Disable USDHC2 clock gate. */
288     CLOCK_DisableClock(kCLOCK_Usdhc2);
289     /* Set USDHC2_PODF. */
290     CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
291     /* Set Usdhc2 clock source. */
292     CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
293     /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
294      * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
295      * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
296 #ifndef SKIP_SYSCLK_INIT
297     /* Disable Semc clock gate. */
298     CLOCK_DisableClock(kCLOCK_Semc);
299     /* Set SEMC_PODF. */
300     CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
301     /* Set Semc alt clock source. */
302     CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
303     /* Set Semc clock source. */
304     CLOCK_SetMux(kCLOCK_SemcMux, 0);
305 #endif
306     /* Disable Flexspi clock gate. */
307     CLOCK_DisableClock(kCLOCK_FlexSpi);
308     /* Set FLEXSPI_PODF. */
309     CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0);
310     /* Set Flexspi clock source. */
311     CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
312     /* In SDK projects, external flash (configured by FLEXSPI2) will be initialized by dcd.
313      * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI2 clock source in SDK projects) will be left unchanged.
314      * Note: If another clock source is selected for FLEXSPI2, user may want to avoid changing that clock as well.*/
315 #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
316     /* Disable Flexspi2 clock gate. */
317     CLOCK_DisableClock(kCLOCK_FlexSpi2);
318     /* Set FLEXSPI2_PODF. */
319     CLOCK_SetDiv(kCLOCK_Flexspi2Div, 0);
320     /* Set Flexspi2 clock source. */
321     CLOCK_SetMux(kCLOCK_Flexspi2Mux, 1);
322 #endif
323     /* Disable CSI clock gate. */
324     CLOCK_DisableClock(kCLOCK_Csi);
325     /* Set CSI_PODF. */
326     CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
327     /* Set Csi clock source. */
328     CLOCK_SetMux(kCLOCK_CsiMux, 0);
329     /* Disable LPSPI clock gate. */
330     CLOCK_DisableClock(kCLOCK_Lpspi1);
331     CLOCK_DisableClock(kCLOCK_Lpspi2);
332     CLOCK_DisableClock(kCLOCK_Lpspi3);
333     CLOCK_DisableClock(kCLOCK_Lpspi4);
334     /* Set LPSPI_PODF. */
335     CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
336     /* Set Lpspi clock source. */
337     CLOCK_SetMux(kCLOCK_LpspiMux, 2);
338     /* Disable TRACE clock gate. */
339     CLOCK_DisableClock(kCLOCK_Trace);
340     /* Set TRACE_PODF. */
341     CLOCK_SetDiv(kCLOCK_TraceDiv, 2);
342     /* Set Trace clock source. */
343     CLOCK_SetMux(kCLOCK_TraceMux, 2);
344     /* Disable SAI1 clock gate. */
345     CLOCK_DisableClock(kCLOCK_Sai1);
346     /* Set SAI1_CLK_PRED. */
347     CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
348     /* Set SAI1_CLK_PODF. */
349     CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
350     /* Set Sai1 clock source. */
351     CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
352     /* Disable SAI2 clock gate. */
353     CLOCK_DisableClock(kCLOCK_Sai2);
354     /* Set SAI2_CLK_PRED. */
355     CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
356     /* Set SAI2_CLK_PODF. */
357     CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
358     /* Set Sai2 clock source. */
359     CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
360     /* Disable SAI3 clock gate. */
361     CLOCK_DisableClock(kCLOCK_Sai3);
362     /* Set SAI3_CLK_PRED. */
363     CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
364     /* Set SAI3_CLK_PODF. */
365     CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
366     /* Set Sai3 clock source. */
367     CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
368     /* Disable Lpi2c clock gate. */
369     CLOCK_DisableClock(kCLOCK_Lpi2c1);
370     CLOCK_DisableClock(kCLOCK_Lpi2c2);
371     CLOCK_DisableClock(kCLOCK_Lpi2c3);
372     /* Set LPI2C_CLK_PODF. */
373     CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
374     /* Set Lpi2c clock source. */
375     CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
376     /* Disable CAN clock gate. */
377     CLOCK_DisableClock(kCLOCK_Can1);
378     CLOCK_DisableClock(kCLOCK_Can2);
379     CLOCK_DisableClock(kCLOCK_Can3);
380     CLOCK_DisableClock(kCLOCK_Can1S);
381     CLOCK_DisableClock(kCLOCK_Can2S);
382     CLOCK_DisableClock(kCLOCK_Can3S);
383     /* Set CAN_CLK_PODF. */
384     CLOCK_SetDiv(kCLOCK_CanDiv, 1);
385     /* Set Can clock source. */
386     CLOCK_SetMux(kCLOCK_CanMux, 2);
387     /* Disable UART clock gate. */
388     CLOCK_DisableClock(kCLOCK_Lpuart1);
389     CLOCK_DisableClock(kCLOCK_Lpuart2);
390     CLOCK_DisableClock(kCLOCK_Lpuart3);
391     CLOCK_DisableClock(kCLOCK_Lpuart4);
392     CLOCK_DisableClock(kCLOCK_Lpuart5);
393     CLOCK_DisableClock(kCLOCK_Lpuart6);
394     CLOCK_DisableClock(kCLOCK_Lpuart7);
395     CLOCK_DisableClock(kCLOCK_Lpuart8);
396     /* Set UART_CLK_PODF. */
397     CLOCK_SetDiv(kCLOCK_UartDiv, 0);
398     /* Set Uart clock source. */
399     CLOCK_SetMux(kCLOCK_UartMux, 0);
400     /* Disable LCDIF clock gate. */
401     CLOCK_DisableClock(kCLOCK_LcdPixel);
402     /* Set LCDIF_PRED. */
403     CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
404     /* Set LCDIF_CLK_PODF. */
405     CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
406     /* Set Lcdif pre clock source. */
407     CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
408     /* Disable SPDIF clock gate. */
409     CLOCK_DisableClock(kCLOCK_Spdif);
410     /* Set SPDIF0_CLK_PRED. */
411     CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
412     /* Set SPDIF0_CLK_PODF. */
413     CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
414     /* Set Spdif clock source. */
415     CLOCK_SetMux(kCLOCK_SpdifMux, 3);
416     /* Disable Flexio1 clock gate. */
417     CLOCK_DisableClock(kCLOCK_Flexio1);
418     /* Set FLEXIO1_CLK_PRED. */
419     CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
420     /* Set FLEXIO1_CLK_PODF. */
421     CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
422     /* Set Flexio1 clock source. */
423     CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
424     /* Disable Flexio2 clock gate. */
425     CLOCK_DisableClock(kCLOCK_Flexio2);
426     /* Set FLEXIO2_CLK_PRED. */
427     CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
428     /* Set FLEXIO2_CLK_PODF. */
429     CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
430     /* Set Flexio2 clock source. */
431     CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
432     /* Set Pll3 sw clock source. */
433     CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
434     /* Set lvds1 clock source. */
435     CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
436     /* Set clock out1 divider. */
437     CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
438     /* Set clock out1 source. */
439     CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
440     /* Set clock out2 divider. */
441     CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
442     /* Set clock out2 source. */
443     CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
444     /* Set clock out1 drives clock out1. */
445     CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
446     /* Disable clock out1. */
447     CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
448     /* Disable clock out2. */
449     CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
450     /* Set SystemCoreClock variable. */
451     SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
452 }
453 
454