1#! armcc -E
2/*
3** ###################################################################
4**     Processors:          MIMXRT1064DVL6A
5**
6**     Compiler:            Keil ARM C/C++ Compiler
7**     Reference manual:    IMXRT1064RM Rev.C, 08/2017
8**     Version:             rev. 0.1, 2019-05-29
9**     Build:               b190529
10**
11**     Abstract:
12**         Linker file for the Keil ARM C/C++ Compiler
13**
14**     Copyright 2016 Freescale Semiconductor, Inc.
15**     Copyright 2016-2017 NXP
16**     Redistribution and use in source and binary forms, with or without modification,
17**     are permitted provided that the following conditions are met:
18**
19**     1. Redistributions of source code must retain the above copyright notice, this list
20**       of conditions and the following disclaimer.
21**
22**     2. Redistributions in binary form must reproduce the above copyright notice, this
23**       list of conditions and the following disclaimer in the documentation and/or
24**       other materials provided with the distribution.
25**
26**     3. Neither the name of the copyright holder nor the names of its
27**       contributors may be used to endorse or promote products derived from this
28**       software without specific prior written permission.
29**
30**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
31**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
32**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
33**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
34**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
35**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
36**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
37**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
39**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40**
41**     http:                 www.nxp.com
42**     mail:                 support@nxp.com
43**
44** ###################################################################
45*/
46
47
48#define m_flash_config_start           0x70000000
49#define m_flash_config_size            0x00001000
50
51#define m_ivt_start                    0x70001000
52#define m_ivt_size                     0x00001000
53
54#define m_interrupts_start             0x70002000
55#define m_interrupts_size              0x00000400
56
57#define m_text_start                   0x70002400
58#define m_text_size                    0x003FDC00
59
60#define m_data_start                   0x20000000       ; DTCM 128KB
61#define m_data_size                    0x00020000
62
63#define m_data2_start                  0x20200000       ; OCRAM2 768KB
64#define m_data2_size                   0x000C0000
65
66#define m_data3_start                  0x00000000       ; ITCM 128KB
67#define m_data3_size                   0x00020000
68
69#define m_ncache_start                 0x81E00000
70#define m_ncache_size                  0x00200000
71
72/* Sizes */
73#if (defined(__stack_size__))
74  #define Stack_Size                   __stack_size__
75#else
76  #define Stack_Size                   0x0400
77#endif
78
79#if (defined(__heap_size__))
80  #define Heap_Size                    __heap_size__
81#else
82  #define Heap_Size                    0x0400
83#endif
84
85#include "../../rtconfig.h"
86
87#if (defined(BSP_USING_4MFLASH))
88LR_m_rom_config m_flash_config_start m_flash_config_size      ; load region size_region
89{
90    RW_m_config_text m_flash_config_start m_flash_config_size ; load address = execution address
91    {
92        * (.boot_hdr.conf, +FIRST)
93    }
94}
95
96LR_m_rom_ivt m_ivt_start m_ivt_size ; load region size_region
97{
98    RW_m_ivt_text m_ivt_start m_ivt_size ; load address = execution address
99    {
100        * (.boot_hdr.ivt, +FIRST)
101        * (.boot_hdr.boot_data)
102        * (.boot_hdr.dcd_data)
103    }
104}
105#endif
106
107#define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK))
108
109; load region size_region
110LR_IROM1 m_text_start m_text_size
111{
112    ER_IROM1 m_text_start m_text_size ; load address = execution address
113    {
114        * (RESET,+FIRST)
115        * (InRoot$$Sections)
116        .ANY (+RO)
117    }
118
119    RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size ; RW data
120    {
121        .ANY (+RW +ZI)
122    }
123
124    ARM_LIB_HEAP +0 EMPTY Heap_Size{}   ; Heap region growing up
125    ARM_LIB_STACK +0 EMPTY Stack_Size{} ; Stack region growing down
126    RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{}
127
128    ; ncache RW data
129    RW_m_ncache m_ncache_start m_ncache_size
130    {
131        * (NonCacheable.init)
132        * (NonCacheable)
133    }
134;  ITCM 0x400 0xFBFF {
135;        ;drv_flexspi_hyper.o(+RO)
136;        ;fsl_flexspi.o(+RO)
137;        * (*CLOCK_DisableClock)
138;        * (*CLOCK_ControlGate)
139;        * (*CLOCK_EnableClock)
140;        * (*CLOCK_SetDiv)
141;        * (itcm)
142;    }
143}
144