1<?xml version="1.0" encoding= "UTF-8" ?> 2<configuration name="" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_12 http://mcuxpresso.nxp.com/XSD/mex_configuration_12.xsd" uuid="2789973b-4e08-461b-a604-ca74c2c2a2cf" version="12" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_12" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> 3 <common> 4 <processor>MIMXRT1176xxxxx</processor> 5 <package>MIMXRT1176DVMAA</package> 6 <mcu_data>ksdk2_0</mcu_data> 7 <cores selected="cm7"> 8 <core name="Cortex-M4F" id="cm4" description=""/> 9 <core name="Cortex-M7F" id="cm7" description=""/> 10 </cores> 11 <description></description> 12 </common> 13 <preferences> 14 <validate_boot_init_only>true</validate_boot_init_only> 15 <generate_extended_information>false</generate_extended_information> 16 <generate_code_modified_registers_only>false</generate_code_modified_registers_only> 17 <update_include_paths>true</update_include_paths> 18 <generate_registers_defines>false</generate_registers_defines> 19 </preferences> 20 <tools> 21 <pins name="Pins" version="12.0" enabled="true" update_project_code="true"> 22 <pins_profile> 23 <processor_version>12.0.0</processor_version> 24 <power_domains/> 25 </pins_profile> 26 <functions_list> 27 <function name="BOARD_InitPins"> 28 <description>Configures pin routing and optionally pin electrical features.</description> 29 <options> 30 <callFromInitBoot>true</callFromInitBoot> 31 <coreID>cm7</coreID> 32 <enableClock>true</enableClock> 33 </options> 34 <dependencies> 35 <dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitPins"> 36 <feature name="initialized" evaluation="equal"> 37 <data>true</data> 38 </feature> 39 </dependency> 40 <dependency resourceType="Peripheral" resourceId="ARM" description="Peripheral ARM is not initialized" problem_level="1" source="Pins:BOARD_InitPins"> 41 <feature name="initialized" evaluation="equal"> 42 <data>true</data> 43 </feature> 44 </dependency> 45 <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins"> 46 <feature name="enabled" evaluation="equal" configuration="cm7"> 47 <data>true</data> 48 </feature> 49 </dependency> 50 <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitPins"> 51 <feature name="enabled" evaluation="equal" configuration="cm7"> 52 <data>true</data> 53 </feature> 54 </dependency> 55 </dependencies> 56 <pins> 57 <pin peripheral="LPUART1" signal="RXD" pin_num="M15" pin_signal="GPIO_AD_25"> 58 <pin_features> 59 <pin_feature name="software_input_on" value="Disable"/> 60 <pin_feature name="pull_up_down_config" value="Pull_Down"/> 61 <pin_feature name="pull_keeper_select" value="Keeper"/> 62 <pin_feature name="open_drain" value="Disable"/> 63 <pin_feature name="drive_strength" value="High"/> 64 <pin_feature name="slew_rate" value="Slow"/> 65 </pin_features> 66 </pin> 67 <pin peripheral="LPUART1" signal="TXD" pin_num="L13" pin_signal="GPIO_AD_24"> 68 <pin_features> 69 <pin_feature name="software_input_on" value="Disable"/> 70 <pin_feature name="pull_up_down_config" value="Pull_Down"/> 71 <pin_feature name="pull_keeper_select" value="Keeper"/> 72 <pin_feature name="open_drain" value="Disable"/> 73 <pin_feature name="drive_strength" value="High"/> 74 <pin_feature name="slew_rate" value="Slow"/> 75 </pin_features> 76 </pin> 77 <pin peripheral="ARM" signal="arm_trace_swo" pin_num="D6" pin_signal="GPIO_DISP_B2_07"> 78 <pin_features> 79 <pin_feature name="software_input_on" value="Disable"/> 80 <pin_feature name="pull_up_down_config" value="Pull_Down"/> 81 <pin_feature name="pull_keeper_select" value="Keeper"/> 82 <pin_feature name="open_drain" value="Disable"/> 83 <pin_feature name="drive_strength" value="High"/> 84 <pin_feature name="slew_rate" value="Slow"/> 85 </pin_features> 86 </pin> 87 </pins> 88 </function> 89 </functions_list> 90 </pins> 91 <clocks name="Clocks" version="10.0" enabled="true" update_project_code="true"> 92 <clocks_profile> 93 <processor_version>12.0.0</processor_version> 94 </clocks_profile> 95 <clock_configurations> 96 <clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false"> 97 <description></description> 98 <options/> 99 <dependencies> 100 <dependency resourceType="PeripheralUnifiedSignal" resourceId="ANADIG.xtali" description="'XTALI' (Pins tool id: ANADIG.xtali, Clocks tool id: ANADIG_OSC.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> 101 <feature name="routed" evaluation=""> 102 <data>true</data> 103 </feature> 104 </dependency> 105 <dependency resourceType="PeripheralUnifiedSignal" resourceId="ANADIG.xtali" description="'XTALI' (Pins tool id: ANADIG.xtali, Clocks tool id: ANADIG_OSC.XTALI) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> 106 <feature name="direction" evaluation=""> 107 <data>INPUT</data> 108 </feature> 109 </dependency> 110 <dependency resourceType="PeripheralUnifiedSignal" resourceId="ANADIG.xtalo" description="'XTALO' (Pins tool id: ANADIG.xtalo, Clocks tool id: ANADIG_OSC.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> 111 <feature name="routed" evaluation=""> 112 <data>true</data> 113 </feature> 114 </dependency> 115 <dependency resourceType="PeripheralUnifiedSignal" resourceId="ANADIG.xtalo" description="'XTALO' (Pins tool id: ANADIG.xtalo, Clocks tool id: ANADIG_OSC.XTALO) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> 116 <feature name="direction" evaluation=""> 117 <data>OUTPUT</data> 118 </feature> 119 </dependency> 120 <dependency resourceType="PeripheralUnifiedSignal" resourceId="ANADIG.rtc_xtali" description="'RTC_XTALI' (Pins tool id: ANADIG.rtc_xtali, Clocks tool id: ANADIG_OSC.RTC_XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> 121 <feature name="routed" evaluation=""> 122 <data>true</data> 123 </feature> 124 </dependency> 125 <dependency resourceType="PeripheralUnifiedSignal" resourceId="ANADIG.rtc_xtali" description="'RTC_XTALI' (Pins tool id: ANADIG.rtc_xtali, Clocks tool id: ANADIG_OSC.RTC_XTALI) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> 126 <feature name="direction" evaluation=""> 127 <data>INPUT</data> 128 </feature> 129 </dependency> 130 <dependency resourceType="PeripheralUnifiedSignal" resourceId="ANADIG.rtc_xtalo" description="'RTC_XTALO' (Pins tool id: ANADIG.rtc_xtalo, Clocks tool id: ANADIG_OSC.RTC_XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> 131 <feature name="routed" evaluation=""> 132 <data>true</data> 133 </feature> 134 </dependency> 135 <dependency resourceType="PeripheralUnifiedSignal" resourceId="ANADIG.rtc_xtalo" description="'RTC_XTALO' (Pins tool id: ANADIG.rtc_xtalo, Clocks tool id: ANADIG_OSC.RTC_XTALO) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> 136 <feature name="direction" evaluation=""> 137 <data>OUTPUT</data> 138 </feature> 139 </dependency> 140 <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> 141 <feature name="enabled" evaluation="equal" configuration="cm4"> 142 <data>true</data> 143 </feature> 144 </dependency> 145 <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> 146 <feature name="enabled" evaluation="equal" configuration="cm7"> 147 <data>true</data> 148 </feature> 149 </dependency> 150 <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> 151 <feature name="enabled" evaluation="equal" configuration="cm4"> 152 <data>true</data> 153 </feature> 154 </dependency> 155 <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> 156 <feature name="enabled" evaluation="equal" configuration="cm7"> 157 <data>true</data> 158 </feature> 159 </dependency> 160 <dependency resourceType="SWComponent" resourceId="platform.drivers.dcdc_soc" description="Clocks initialization requires the DCDC_SOC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> 161 <feature name="enabled" evaluation="equal" configuration="cm4"> 162 <data>true</data> 163 </feature> 164 </dependency> 165 <dependency resourceType="SWComponent" resourceId="platform.drivers.dcdc_soc" description="Clocks initialization requires the DCDC_SOC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> 166 <feature name="enabled" evaluation="equal" configuration="cm7"> 167 <data>true</data> 168 </feature> 169 </dependency> 170 <dependency resourceType="SWComponent" resourceId="platform.drivers.pmu_1" description="Clocks initialization requires the PMU_1 Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> 171 <feature name="enabled" evaluation="equal" configuration="cm4"> 172 <data>true</data> 173 </feature> 174 </dependency> 175 <dependency resourceType="SWComponent" resourceId="platform.drivers.pmu_1" description="Clocks initialization requires the PMU_1 Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> 176 <feature name="enabled" evaluation="equal" configuration="cm7"> 177 <data>true</data> 178 </feature> 179 </dependency> 180 <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> 181 <feature name="enabled" evaluation="equal" configuration="cm4"> 182 <data>true</data> 183 </feature> 184 </dependency> 185 <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> 186 <feature name="enabled" evaluation="equal" configuration="cm7"> 187 <data>true</data> 188 </feature> 189 </dependency> 190 </dependencies> 191 <clock_sources/> 192 <clock_outputs> 193 <clock_output id="ACMP_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 194 <clock_output id="ADC1_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 195 <clock_output id="ADC2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 196 <clock_output id="ARM_PLL_CLK.outFreq" value="996 MHz" locked="false" accuracy=""/> 197 <clock_output id="ASRC_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 198 <clock_output id="AXI_CLK_ROOT.outFreq" value="996 MHz" locked="false" accuracy=""/> 199 <clock_output id="BUS_CLK_ROOT.outFreq" value="240 MHz" locked="false" accuracy=""/> 200 <clock_output id="BUS_LPSR_CLK_ROOT.outFreq" value="160 MHz" locked="false" accuracy=""/> 201 <clock_output id="CAN1_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 202 <clock_output id="CAN2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 203 <clock_output id="CAN3_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 204 <clock_output id="CCM_CLKO1_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 205 <clock_output id="CCM_CLKO2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 206 <clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/> 207 <clock_output id="CSI2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 208 <clock_output id="CSI2_ESC_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 209 <clock_output id="CSI2_UI_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 210 <clock_output id="CSI_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 211 <clock_output id="CSSYS_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 212 <clock_output id="CSTRACE_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/> 213 <clock_output id="ELCDIF_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 214 <clock_output id="EMV1_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 215 <clock_output id="EMV2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 216 <clock_output id="ENET1_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 217 <clock_output id="ENET2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 218 <clock_output id="ENET_1G_TX_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/> 219 <clock_output id="ENET_25M_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 220 <clock_output id="ENET_QOS_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 221 <clock_output id="ENET_TIMER1_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 222 <clock_output id="ENET_TIMER2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 223 <clock_output id="ENET_TIMER3_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 224 <clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 225 <clock_output id="FLEXIO2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 226 <clock_output id="FLEXSPI1_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 227 <clock_output id="FLEXSPI2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 228 <clock_output id="GC355_CLK_ROOT.outFreq" value="492.0000125 MHz" locked="false" accuracy=""/> 229 <clock_output id="GPT1_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 230 <clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="24 MHz" locked="false" accuracy=""/> 231 <clock_output id="GPT2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 232 <clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="24 MHz" locked="false" accuracy=""/> 233 <clock_output id="GPT3_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 234 <clock_output id="GPT3_ipg_clk_highfreq.outFreq" value="24 MHz" locked="false" accuracy=""/> 235 <clock_output id="GPT4_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 236 <clock_output id="GPT4_ipg_clk_highfreq.outFreq" value="24 MHz" locked="false" accuracy=""/> 237 <clock_output id="GPT5_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 238 <clock_output id="GPT5_ipg_clk_highfreq.outFreq" value="24 MHz" locked="false" accuracy=""/> 239 <clock_output id="GPT6_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 240 <clock_output id="GPT6_ipg_clk_highfreq.outFreq" value="24 MHz" locked="false" accuracy=""/> 241 <clock_output id="LCDIFV2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 242 <clock_output id="LPI2C1_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 243 <clock_output id="LPI2C2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 244 <clock_output id="LPI2C3_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 245 <clock_output id="LPI2C4_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 246 <clock_output id="LPI2C5_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 247 <clock_output id="LPI2C6_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 248 <clock_output id="LPSPI1_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 249 <clock_output id="LPSPI2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 250 <clock_output id="LPSPI3_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 251 <clock_output id="LPSPI4_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 252 <clock_output id="LPSPI5_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 253 <clock_output id="LPSPI6_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 254 <clock_output id="LPUART10_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 255 <clock_output id="LPUART11_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 256 <clock_output id="LPUART12_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 257 <clock_output id="LPUART1_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 258 <clock_output id="LPUART2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 259 <clock_output id="LPUART3_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 260 <clock_output id="LPUART4_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 261 <clock_output id="LPUART5_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 262 <clock_output id="LPUART6_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 263 <clock_output id="LPUART7_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 264 <clock_output id="LPUART8_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 265 <clock_output id="LPUART9_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 266 <clock_output id="M4_CLK_ROOT.outFreq" value="240 MHz" locked="false" accuracy=""/> 267 <clock_output id="M4_SYSTICK_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 268 <clock_output id="M7_CLK_ROOT.outFreq" value="996 MHz" locked="false" accuracy=""/> 269 <clock_output id="M7_SYSTICK_CLK_ROOT.outFreq" value="100 kHz" locked="false" accuracy=""/> 270 <clock_output id="MIC_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 271 <clock_output id="MIPI_DSI_TX_CLK_ESC_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 272 <clock_output id="MIPI_ESC_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 273 <clock_output id="MIPI_REF_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 274 <clock_output id="MQS_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 275 <clock_output id="MQS_MCLK.outFreq" value="24 MHz" locked="false" accuracy=""/> 276 <clock_output id="OSC_24M.outFreq" value="24 MHz" locked="false" accuracy=""/> 277 <clock_output id="OSC_32K.outFreq" value="32.768 kHz" locked="false" accuracy=""/> 278 <clock_output id="OSC_RC_16M.outFreq" value="16 MHz" locked="false" accuracy=""/> 279 <clock_output id="OSC_RC_400M.outFreq" value="400 MHz" locked="false" accuracy=""/> 280 <clock_output id="OSC_RC_48M.outFreq" value="48 MHz" locked="false" accuracy=""/> 281 <clock_output id="OSC_RC_48M_DIV2.outFreq" value="24 MHz" locked="false" accuracy=""/> 282 <clock_output id="PLL_VIDEO_CLK.outFreq" value="984.000025 MHz" locked="false" accuracy=""/> 283 <clock_output id="SAI1_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 284 <clock_output id="SAI1_MCLK1.outFreq" value="24 MHz" locked="false" accuracy=""/> 285 <clock_output id="SAI1_MCLK3.outFreq" value="24 MHz" locked="false" accuracy=""/> 286 <clock_output id="SAI2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 287 <clock_output id="SAI2_MCLK1.outFreq" value="24 MHz" locked="false" accuracy=""/> 288 <clock_output id="SAI2_MCLK3.outFreq" value="24 MHz" locked="false" accuracy=""/> 289 <clock_output id="SAI3_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 290 <clock_output id="SAI3_MCLK1.outFreq" value="24 MHz" locked="false" accuracy=""/> 291 <clock_output id="SAI3_MCLK3.outFreq" value="24 MHz" locked="false" accuracy=""/> 292 <clock_output id="SAI4_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 293 <clock_output id="SAI4_MCLK1.outFreq" value="24 MHz" locked="false" accuracy=""/> 294 <clock_output id="SEMC_CLK_ROOT.outFreq" value="198 MHz" locked="false" accuracy=""/> 295 <clock_output id="SPDIF_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 296 <clock_output id="SYS_PLL2_CLK.outFreq" value="528 MHz" locked="false" accuracy=""/> 297 <clock_output id="SYS_PLL2_PFD0_CLK.outFreq" value="352 MHz" locked="false" accuracy=""/> 298 <clock_output id="SYS_PLL2_PFD1_CLK.outFreq" value="594 MHz" locked="false" accuracy=""/> 299 <clock_output id="SYS_PLL2_PFD2_CLK.outFreq" value="396 MHz" locked="false" accuracy=""/> 300 <clock_output id="SYS_PLL2_PFD3_CLK.outFreq" value="297 MHz" locked="false" accuracy=""/> 301 <clock_output id="SYS_PLL3_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/> 302 <clock_output id="SYS_PLL3_DIV2_CLK.outFreq" value="240 MHz" locked="false" accuracy=""/> 303 <clock_output id="SYS_PLL3_PFD0_CLK.outFreq" value="8640/13 MHz" locked="false" accuracy=""/> 304 <clock_output id="SYS_PLL3_PFD1_CLK.outFreq" value="8640/17 MHz" locked="false" accuracy=""/> 305 <clock_output id="SYS_PLL3_PFD2_CLK.outFreq" value="270 MHz" locked="false" accuracy=""/> 306 <clock_output id="SYS_PLL3_PFD3_CLK.outFreq" value="4320/11 MHz" locked="false" accuracy=""/> 307 <clock_output id="USDHC1_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 308 <clock_output id="USDHC2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/> 309 </clock_outputs> 310 <clock_settings> 311 <setting id="CoreBusClockRootsInitializationConfig" value="selectedCore" locked="false"/> 312 <setting id="SOCDomainVoltage" value="OD" locked="false"/> 313 <setting id="ANADIG_OSC_OSC_24M_CTRL_LP_EN_CFG" value="Low" locked="false"/> 314 <setting id="ANADIG_OSC_OSC_24M_CTRL_OSC_EN_CFG" value="Enabled" locked="false"/> 315 <setting id="ANADIG_PLL.PLL_AUDIO_BYPASS.sel" value="ANADIG_OSC.OSC_24M" locked="false"/> 316 <setting id="ANADIG_PLL.PLL_VIDEO.denom" value="960000" locked="false"/> 317 <setting id="ANADIG_PLL.PLL_VIDEO.div" value="41" locked="false"/> 318 <setting id="ANADIG_PLL.PLL_VIDEO.num" value="1" locked="false"/> 319 <setting id="ANADIG_PLL.SYS_PLL1_BYPASS.sel" value="ANADIG_OSC.OSC_24M" locked="false"/> 320 <setting id="ANADIG_PLL.SYS_PLL2.denom" value="268435455" locked="false"/> 321 <setting id="ANADIG_PLL.SYS_PLL2.div" value="22" locked="false"/> 322 <setting id="ANADIG_PLL.SYS_PLL2.num" value="0" locked="false"/> 323 <setting id="ANADIG_PLL.SYS_PLL2_SS_DIV.scale" value="268435455" locked="false"/> 324 <setting id="ANADIG_PLL.SYS_PLL3_PFD3_DIV.scale" value="22" locked="true"/> 325 <setting id="ANADIG_PLL.SYS_PLL3_PFD3_MUL.scale" value="18" locked="true"/> 326 <setting id="ANADIG_PLL_ARM_PLL_CTRL_POWERUP_CFG" value="Enabled" locked="false"/> 327 <setting id="ANADIG_PLL_PLL_AUDIO_CTRL_GATE_CFG" value="Disabled" locked="false"/> 328 <setting id="ANADIG_PLL_PLL_VIDEO_CTRL0_POWERUP_CFG" value="Enabled" locked="false"/> 329 <setting id="ANADIG_PLL_SYS_PLL1_CTRL0_POWERUP_CFG" value="Disabled" locked="false"/> 330 <setting id="ANADIG_PLL_SYS_PLL1_CTRL_GATE_CFG" value="Disabled" locked="false"/> 331 <setting id="ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_CFG" value="Enabled" locked="false"/> 332 <setting id="ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_CFG" value="Enabled" locked="false"/> 333 <setting id="ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CFG" value="Enabled" locked="false"/> 334 <setting id="CCM.CLOCK_ROOT0.MUX.sel" value="ANADIG_PLL.ARM_PLL_CLK" locked="false"/> 335 <setting id="CCM.CLOCK_ROOT1.DIV.scale" value="2" locked="true"/> 336 <setting id="CCM.CLOCK_ROOT1.MUX.sel" value="ANADIG_PLL.SYS_PLL3_CLK" locked="false"/> 337 <setting id="CCM.CLOCK_ROOT2.DIV.scale" value="2" locked="false"/> 338 <setting id="CCM.CLOCK_ROOT2.MUX.sel" value="ANADIG_PLL.SYS_PLL3_CLK" locked="false"/> 339 <setting id="CCM.CLOCK_ROOT25.DIV.scale" value="22" locked="false"/> 340 <setting id="CCM.CLOCK_ROOT25.MUX.sel" value="ANADIG_PLL.SYS_PLL2_CLK" locked="false"/> 341 <setting id="CCM.CLOCK_ROOT26.DIV.scale" value="22" locked="false"/> 342 <setting id="CCM.CLOCK_ROOT26.MUX.sel" value="ANADIG_PLL.SYS_PLL2_CLK" locked="false"/> 343 <setting id="CCM.CLOCK_ROOT3.DIV.scale" value="3" locked="false"/> 344 <setting id="CCM.CLOCK_ROOT3.MUX.sel" value="ANADIG_PLL.SYS_PLL3_CLK" locked="false"/> 345 <setting id="CCM.CLOCK_ROOT4.DIV.scale" value="3" locked="false"/> 346 <setting id="CCM.CLOCK_ROOT4.MUX.sel" value="ANADIG_PLL.SYS_PLL2_PFD1_CLK" locked="false"/> 347 <setting id="CCM.CLOCK_ROOT6.DIV.scale" value="4" locked="true"/> 348 <setting id="CCM.CLOCK_ROOT6.MUX.sel" value="ANADIG_PLL.SYS_PLL2_CLK" locked="false"/> 349 <setting id="CCM.CLOCK_ROOT68.DIV.scale" value="2" locked="false"/> 350 <setting id="CCM.CLOCK_ROOT68.MUX.sel" value="ANADIG_PLL.PLL_VIDEO_CLK" locked="false"/> 351 <setting id="CCM.CLOCK_ROOT8.DIV.scale" value="240" locked="false"/> 352 </clock_settings> 353 <called_from_default_init>true</called_from_default_init> 354 </clock_configuration> 355 </clock_configurations> 356 </clocks> 357 <dcdx name="DCDx" version="3.0" enabled="true" update_project_code="true"> 358 <dcdx_profile> 359 <processor_version>12.0.0</processor_version> 360 <output_format>c_array</output_format> 361 </dcdx_profile> 362 <dcdx_configurations> 363 <dcdx_configuration name="Device_configuration"> 364 <description></description> 365 <options/> 366 <command_groups> 367 <command_group name="Imported Commands" enabled="true"> 368 <commands> 369 <command type="write_value" address="CCM_CLOCK_ROOT4_CONTROL" value="0x602" value_width="4"/> 370 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_00" value="0x00" value_width="4"/> 371 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_01" value="0x00" value_width="4"/> 372 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_02" value="0x00" value_width="4"/> 373 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_03" value="0x00" value_width="4"/> 374 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_04" value="0x00" value_width="4"/> 375 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_05" value="0x00" value_width="4"/> 376 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_06" value="0x00" value_width="4"/> 377 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_07" value="0x00" value_width="4"/> 378 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_08" value="0x00" value_width="4"/> 379 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_09" value="0x00" value_width="4"/> 380 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_10" value="0x00" value_width="4"/> 381 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_11" value="0x00" value_width="4"/> 382 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_12" value="0x00" value_width="4"/> 383 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_13" value="0x00" value_width="4"/> 384 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_14" value="0x00" value_width="4"/> 385 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_15" value="0x00" value_width="4"/> 386 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_16" value="0x00" value_width="4"/> 387 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_17" value="0x00" value_width="4"/> 388 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_18" value="0x00" value_width="4"/> 389 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_19" value="0x00" value_width="4"/> 390 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_20" value="0x00" value_width="4"/> 391 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_21" value="0x00" value_width="4"/> 392 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_22" value="0x00" value_width="4"/> 393 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_23" value="0x00" value_width="4"/> 394 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_24" value="0x00" value_width="4"/> 395 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_25" value="0x00" value_width="4"/> 396 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_26" value="0x00" value_width="4"/> 397 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_27" value="0x00" value_width="4"/> 398 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_28" value="0x00" value_width="4"/> 399 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_29" value="0x00" value_width="4"/> 400 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_30" value="0x00" value_width="4"/> 401 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_31" value="0x00" value_width="4"/> 402 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_32" value="0x00" value_width="4"/> 403 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_33" value="0x00" value_width="4"/> 404 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_34" value="0x00" value_width="4"/> 405 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_35" value="0x00" value_width="4"/> 406 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_36" value="0x00" value_width="4"/> 407 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_37" value="0x00" value_width="4"/> 408 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_38" value="0x00" value_width="4"/> 409 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_39" value="0x10" value_width="4"/> 410 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_40" value="0x00" value_width="4"/> 411 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_41" value="0x00" value_width="4"/> 412 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_00" value="0x00" value_width="4"/> 413 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_01" value="0x00" value_width="4"/> 414 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_02" value="0x00" value_width="4"/> 415 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_03" value="0x00" value_width="4"/> 416 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_04" value="0x00" value_width="4"/> 417 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_05" value="0x00" value_width="4"/> 418 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_06" value="0x00" value_width="4"/> 419 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_07" value="0x00" value_width="4"/> 420 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_08" value="0x00" value_width="4"/> 421 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_09" value="0x00" value_width="4"/> 422 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_10" value="0x00" value_width="4"/> 423 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_11" value="0x00" value_width="4"/> 424 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_12" value="0x00" value_width="4"/> 425 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_13" value="0x00" value_width="4"/> 426 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_14" value="0x00" value_width="4"/> 427 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_15" value="0x00" value_width="4"/> 428 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_16" value="0x00" value_width="4"/> 429 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_17" value="0x00" value_width="4"/> 430 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_18" value="0x00" value_width="4"/> 431 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_19" value="0x00" value_width="4"/> 432 <command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_20" value="0x00" value_width="4"/> 433 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_00" value="0x08" value_width="4"/> 434 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_01" value="0x08" value_width="4"/> 435 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_02" value="0x08" value_width="4"/> 436 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_03" value="0x08" value_width="4"/> 437 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_04" value="0x08" value_width="4"/> 438 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_05" value="0x08" value_width="4"/> 439 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_06" value="0x08" value_width="4"/> 440 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_07" value="0x08" value_width="4"/> 441 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_08" value="0x08" value_width="4"/> 442 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_09" value="0x08" value_width="4"/> 443 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_10" value="0x08" value_width="4"/> 444 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_11" value="0x08" value_width="4"/> 445 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_12" value="0x08" value_width="4"/> 446 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_13" value="0x08" value_width="4"/> 447 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_14" value="0x08" value_width="4"/> 448 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_15" value="0x08" value_width="4"/> 449 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_16" value="0x08" value_width="4"/> 450 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_17" value="0x08" value_width="4"/> 451 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_18" value="0x08" value_width="4"/> 452 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_19" value="0x08" value_width="4"/> 453 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_20" value="0x08" value_width="4"/> 454 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_21" value="0x08" value_width="4"/> 455 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_22" value="0x08" value_width="4"/> 456 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_23" value="0x08" value_width="4"/> 457 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_24" value="0x08" value_width="4"/> 458 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_25" value="0x08" value_width="4"/> 459 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_26" value="0x08" value_width="4"/> 460 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_27" value="0x08" value_width="4"/> 461 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_28" value="0x08" value_width="4"/> 462 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_29" value="0x08" value_width="4"/> 463 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_30" value="0x08" value_width="4"/> 464 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_31" value="0x08" value_width="4"/> 465 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_32" value="0x08" value_width="4"/> 466 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_33" value="0x08" value_width="4"/> 467 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_34" value="0x08" value_width="4"/> 468 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_35" value="0x08" value_width="4"/> 469 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_36" value="0x08" value_width="4"/> 470 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_37" value="0x08" value_width="4"/> 471 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_38" value="0x08" value_width="4"/> 472 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_39" value="0x08" value_width="4"/> 473 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_40" value="0x08" value_width="4"/> 474 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_41" value="0x08" value_width="4"/> 475 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_00" value="0x08" value_width="4"/> 476 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_01" value="0x08" value_width="4"/> 477 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_02" value="0x08" value_width="4"/> 478 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_03" value="0x08" value_width="4"/> 479 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_04" value="0x08" value_width="4"/> 480 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_05" value="0x08" value_width="4"/> 481 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_06" value="0x08" value_width="4"/> 482 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_07" value="0x08" value_width="4"/> 483 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_08" value="0x08" value_width="4"/> 484 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_09" value="0x08" value_width="4"/> 485 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_10" value="0x08" value_width="4"/> 486 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_11" value="0x08" value_width="4"/> 487 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_12" value="0x08" value_width="4"/> 488 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_13" value="0x08" value_width="4"/> 489 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_14" value="0x08" value_width="4"/> 490 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_15" value="0x08" value_width="4"/> 491 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_16" value="0x08" value_width="4"/> 492 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_02" value="0x08" value_width="4"/> 493 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_03" value="0x08" value_width="4"/> 494 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_04" value="0x08" value_width="4"/> 495 <command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_05" value="0x08" value_width="4"/> 496 <command type="write_value" address="SEMC_MCR" value="0x10000004" value_width="4"/> 497 <command type="write_value" address="SEMC_BMCR0" value="0x81" value_width="4"/> 498 <command type="write_value" address="SEMC_BMCR1" value="0x81" value_width="4"/> 499 <command type="write_value" address="SEMC_BR0" value="0x8000001D" value_width="4"/> 500 <command type="write_value" address="SEMC_SDRAMCR0" value="0xF32" value_width="4"/> 501 <command type="write_value" address="SEMC_SDRAMCR1" value="0x772A22" value_width="4"/> 502 <command type="write_value" address="SEMC_SDRAMCR2" value="0x10A0D" value_width="4"/> 503 <command type="write_value" address="SEMC_SDRAMCR3" value="0x21210408" value_width="4"/> 504 <command type="write_value" address="SEMC_IPCR0" value="0x80000000" value_width="4"/> 505 <command type="write_value" address="SEMC_IPCR1" value="0x02" value_width="4"/> 506 <command type="write_value" address="SEMC_IPCR2" value="0x00" value_width="4"/> 507 <command type="write_value" address="SEMC_IPCMD" value="0xA55A000F" value_width="4"/> 508 <command type="nop"/> 509 <command type="nop"/> 510 <command type="nop"/> 511 <command type="nop"/> 512 <command type="nop"/> 513 <command type="write_value" address="SEMC_INTR" value="0x03" value_width="4"/> 514 <command type="write_value" address="SEMC_IPCMD" value="0xA55A000C" value_width="4"/> 515 <command type="nop"/> 516 <command type="nop"/> 517 <command type="nop"/> 518 <command type="nop"/> 519 <command type="nop"/> 520 <command type="write_value" address="SEMC_INTR" value="0x03" value_width="4"/> 521 <command type="write_value" address="SEMC_IPCMD" value="0xA55A000C" value_width="4"/> 522 <command type="nop"/> 523 <command type="nop"/> 524 <command type="nop"/> 525 <command type="nop"/> 526 <command type="nop"/> 527 <command type="write_value" address="SEMC_INTR" value="0x03" value_width="4"/> 528 <command type="write_value" address="SEMC_IPTXDAT" value="0x33" value_width="4"/> 529 <command type="write_value" address="SEMC_IPCMD" value="0xA55A000A" value_width="4"/> 530 <command type="nop"/> 531 <command type="nop"/> 532 <command type="nop"/> 533 <command type="nop"/> 534 <command type="nop"/> 535 <command type="write_value" address="SEMC_INTR" value="0x03" value_width="4"/> 536 <command type="nop"/> 537 <command type="write_value" address="SEMC_SDRAMCR3" value="0x21210409" value_width="4"/> 538 </commands> 539 </command_group> 540 </command_groups> 541 </dcdx_configuration> 542 </dcdx_configurations> 543 </dcdx> 544 <periphs name="Peripherals" version="11.0" enabled="true" update_project_code="true"> 545 <peripherals_profile> 546 <processor_version>12.0.0</processor_version> 547 </peripherals_profile> 548 <functional_groups> 549 <functional_group name="BOARD_InitPeripherals" uuid="7ee8fc36-68c9-403c-a923-44701e1362da" called_from_default_init="true" id_prefix="" core="cm7"> 550 <description></description> 551 <options/> 552 <dependencies/> 553 <instances> 554 <instance name="NVIC" uuid="d4faf8dc-cf39-4bc4-9458-32aa9a8abad5" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false"> 555 <config_set name="nvic"> 556 <array name="interrupt_table"/> 557 <array name="interrupts"/> 558 </config_set> 559 </instance> 560 </instances> 561 </functional_group> 562 </functional_groups> 563 <components> 564 <component name="system" uuid="58d02eb0-c8a1-4795-aa02-b881f9b49f65" type_id="system_54b53072540eeeb8f8e9343e71f28176"> 565 <config_set_global name="global_system_definitions"> 566 <setting name="user_definitions" value=""/> 567 <setting name="user_includes" value=""/> 568 </config_set_global> 569 </component> 570 <component name="msg" uuid="fef81701-6364-47eb-be4e-1ff685c6f487" type_id="msg_6e2baaf3b97dbeef01c0043275f9a0e7"> 571 <config_set_global name="global_messages"/> 572 </component> 573 <component name="generic_uart" uuid="82bb7638-b911-4bff-8d51-e85a18d5f0c8" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6"> 574 <config_set_global name="global_uart"/> 575 </component> 576 <component name="generic_can" uuid="72d70388-6163-458b-9bd7-e49b1b8c0e60" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80"> 577 <config_set_global name="global_can"/> 578 </component> 579 <component name="uart_cmsis_common" uuid="7caa4732-5e54-4482-8d2b-2648eb52adab" type_id="uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8"> 580 <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/> 581 </component> 582 <component name="gpio_adapter_common" uuid="c2f350f4-c700-4bc8-8fb1-aa56fd3533d1" type_id="gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6"> 583 <config_set_global name="global_gpio_adapter_common" quick_selection="default"/> 584 </component> 585 <component name="generic_enet" uuid="77d2c2b6-f8f5-4d79-9870-5662fd323401" type_id="generic_enet_74db5c914f0ddbe47d86af40cb77a619"> 586 <config_set_global name="global_enet"/> 587 </component> 588 </components> 589 </periphs> 590 <tee name="TEE" version="3.0" enabled="false" update_project_code="true"> 591 <tee_profile> 592 <processor_version>N/A</processor_version> 593 </tee_profile> 594 </tee> 595 </tools> 596</configuration>