1 #ifndef _CLOCK_CONFIG_H_ 2 #define _CLOCK_CONFIG_H_ 3 4 #include "fsl_common.h" 5 6 /******************************************************************************* 7 * Definitions 8 ******************************************************************************/ 9 10 #define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ 11 12 #define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ 13 14 /******************************************************************************* 15 ************************ BOARD_InitBootClocks function ************************ 16 ******************************************************************************/ 17 18 #if defined(__cplusplus) 19 extern "C" { 20 #endif /* __cplusplus*/ 21 22 /*! 23 * @brief This function executes default configuration of clocks. 24 * 25 */ 26 void BOARD_InitBootClocks(void); 27 28 #if defined(__cplusplus) 29 } 30 #endif /* __cplusplus*/ 31 32 /******************************************************************************* 33 ********************** Configuration BOARD_BootClockRUN *********************** 34 ******************************************************************************/ 35 /******************************************************************************* 36 * Definitions for BOARD_BootClockRUN configuration 37 ******************************************************************************/ 38 #if __CORTEX_M == 7 39 #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 996000000UL /*!< CM7 Core clock frequency: 996000000Hz */ 40 #else 41 #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 240000000UL /*!< CM4 Core clock frequency: 240000000Hz */ 42 #endif 43 44 /* Clock outputs (values are in Hz): */ 45 #define BOARD_BOOTCLOCKRUN_ACMP_CLK_ROOT 24000000UL 46 #define BOARD_BOOTCLOCKRUN_ADC1_CLK_ROOT 24000000UL 47 #define BOARD_BOOTCLOCKRUN_ADC2_CLK_ROOT 24000000UL 48 #define BOARD_BOOTCLOCKRUN_ARM_PLL_CLK 996000000UL 49 #define BOARD_BOOTCLOCKRUN_ASRC_CLK_ROOT 24000000UL 50 #define BOARD_BOOTCLOCKRUN_AXI_CLK_ROOT 996000000UL 51 #define BOARD_BOOTCLOCKRUN_BUS_CLK_ROOT 240000000UL 52 #define BOARD_BOOTCLOCKRUN_BUS_LPSR_CLK_ROOT 160000000UL 53 #define BOARD_BOOTCLOCKRUN_CAN1_CLK_ROOT 24000000UL 54 #define BOARD_BOOTCLOCKRUN_CAN2_CLK_ROOT 24000000UL 55 #define BOARD_BOOTCLOCKRUN_CAN3_CLK_ROOT 24000000UL 56 #define BOARD_BOOTCLOCKRUN_CCM_CLKO1_CLK_ROOT 24000000UL 57 #define BOARD_BOOTCLOCKRUN_CCM_CLKO2_CLK_ROOT 24000000UL 58 #define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL 59 #define BOARD_BOOTCLOCKRUN_CSI2_CLK_ROOT 24000000UL 60 #define BOARD_BOOTCLOCKRUN_CSI2_ESC_CLK_ROOT 24000000UL 61 #define BOARD_BOOTCLOCKRUN_CSI2_UI_CLK_ROOT 24000000UL 62 #define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 24000000UL 63 #define BOARD_BOOTCLOCKRUN_CSSYS_CLK_ROOT 24000000UL 64 #define BOARD_BOOTCLOCKRUN_CSTRACE_CLK_ROOT 132000000UL 65 #define BOARD_BOOTCLOCKRUN_ELCDIF_CLK_ROOT 24000000UL 66 #define BOARD_BOOTCLOCKRUN_EMV1_CLK_ROOT 24000000UL 67 #define BOARD_BOOTCLOCKRUN_EMV2_CLK_ROOT 24000000UL 68 #define BOARD_BOOTCLOCKRUN_ENET1_CLK_ROOT 24000000UL 69 #define BOARD_BOOTCLOCKRUN_ENET2_CLK_ROOT 24000000UL 70 #define BOARD_BOOTCLOCKRUN_ENET_1G_REF_CLK 0UL 71 #define BOARD_BOOTCLOCKRUN_ENET_1G_TX_CLK 24000000UL 72 #define BOARD_BOOTCLOCKRUN_ENET_25M_CLK_ROOT 24000000UL 73 #define BOARD_BOOTCLOCKRUN_ENET_QOS_CLK_ROOT 24000000UL 74 #define BOARD_BOOTCLOCKRUN_ENET_QOS_REF_CLK 0UL 75 #define BOARD_BOOTCLOCKRUN_ENET_QOS_TX_CLK 0UL 76 #define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL 77 #define BOARD_BOOTCLOCKRUN_ENET_TIMER1_CLK_ROOT 24000000UL 78 #define BOARD_BOOTCLOCKRUN_ENET_TIMER2_CLK_ROOT 24000000UL 79 #define BOARD_BOOTCLOCKRUN_ENET_TIMER3_CLK_ROOT 24000000UL 80 #define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL 81 #define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 24000000UL 82 #define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 24000000UL 83 #define BOARD_BOOTCLOCKRUN_FLEXSPI1_CLK_ROOT 24000000UL 84 #define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 24000000UL 85 #define BOARD_BOOTCLOCKRUN_GC355_CLK_ROOT 492000012UL 86 #define BOARD_BOOTCLOCKRUN_GPT1_CLK_ROOT 24000000UL 87 #define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 24000000UL 88 #define BOARD_BOOTCLOCKRUN_GPT2_CLK_ROOT 24000000UL 89 #define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 24000000UL 90 #define BOARD_BOOTCLOCKRUN_GPT3_CLK_ROOT 24000000UL 91 #define BOARD_BOOTCLOCKRUN_GPT3_IPG_CLK_HIGHFREQ 24000000UL 92 #define BOARD_BOOTCLOCKRUN_GPT4_CLK_ROOT 24000000UL 93 #define BOARD_BOOTCLOCKRUN_GPT4_IPG_CLK_HIGHFREQ 24000000UL 94 #define BOARD_BOOTCLOCKRUN_GPT5_CLK_ROOT 24000000UL 95 #define BOARD_BOOTCLOCKRUN_GPT5_IPG_CLK_HIGHFREQ 24000000UL 96 #define BOARD_BOOTCLOCKRUN_GPT6_CLK_ROOT 24000000UL 97 #define BOARD_BOOTCLOCKRUN_GPT6_IPG_CLK_HIGHFREQ 24000000UL 98 #define BOARD_BOOTCLOCKRUN_LCDIFV2_CLK_ROOT 24000000UL 99 #define BOARD_BOOTCLOCKRUN_LPI2C1_CLK_ROOT 24000000UL 100 #define BOARD_BOOTCLOCKRUN_LPI2C2_CLK_ROOT 24000000UL 101 #define BOARD_BOOTCLOCKRUN_LPI2C3_CLK_ROOT 24000000UL 102 #define BOARD_BOOTCLOCKRUN_LPI2C4_CLK_ROOT 24000000UL 103 #define BOARD_BOOTCLOCKRUN_LPI2C5_CLK_ROOT 24000000UL 104 #define BOARD_BOOTCLOCKRUN_LPI2C6_CLK_ROOT 24000000UL 105 #define BOARD_BOOTCLOCKRUN_LPSPI1_CLK_ROOT 24000000UL 106 #define BOARD_BOOTCLOCKRUN_LPSPI2_CLK_ROOT 24000000UL 107 #define BOARD_BOOTCLOCKRUN_LPSPI3_CLK_ROOT 24000000UL 108 #define BOARD_BOOTCLOCKRUN_LPSPI4_CLK_ROOT 24000000UL 109 #define BOARD_BOOTCLOCKRUN_LPSPI5_CLK_ROOT 24000000UL 110 #define BOARD_BOOTCLOCKRUN_LPSPI6_CLK_ROOT 24000000UL 111 #define BOARD_BOOTCLOCKRUN_LPUART10_CLK_ROOT 24000000UL 112 #define BOARD_BOOTCLOCKRUN_LPUART11_CLK_ROOT 24000000UL 113 #define BOARD_BOOTCLOCKRUN_LPUART12_CLK_ROOT 24000000UL 114 #define BOARD_BOOTCLOCKRUN_LPUART1_CLK_ROOT 24000000UL 115 #define BOARD_BOOTCLOCKRUN_LPUART2_CLK_ROOT 24000000UL 116 #define BOARD_BOOTCLOCKRUN_LPUART3_CLK_ROOT 24000000UL 117 #define BOARD_BOOTCLOCKRUN_LPUART4_CLK_ROOT 24000000UL 118 #define BOARD_BOOTCLOCKRUN_LPUART5_CLK_ROOT 24000000UL 119 #define BOARD_BOOTCLOCKRUN_LPUART6_CLK_ROOT 24000000UL 120 #define BOARD_BOOTCLOCKRUN_LPUART7_CLK_ROOT 24000000UL 121 #define BOARD_BOOTCLOCKRUN_LPUART8_CLK_ROOT 24000000UL 122 #define BOARD_BOOTCLOCKRUN_LPUART9_CLK_ROOT 24000000UL 123 #define BOARD_BOOTCLOCKRUN_M4_CLK_ROOT 240000000UL 124 #define BOARD_BOOTCLOCKRUN_M4_SYSTICK_CLK_ROOT 24000000UL 125 #define BOARD_BOOTCLOCKRUN_M7_CLK_ROOT 996000000UL 126 #define BOARD_BOOTCLOCKRUN_M7_SYSTICK_CLK_ROOT 100000UL 127 #define BOARD_BOOTCLOCKRUN_MIC_CLK_ROOT 24000000UL 128 #define BOARD_BOOTCLOCKRUN_MIPI_DSI_TX_CLK_ESC_ROOT 24000000UL 129 #define BOARD_BOOTCLOCKRUN_MIPI_ESC_CLK_ROOT 24000000UL 130 #define BOARD_BOOTCLOCKRUN_MIPI_REF_CLK_ROOT 24000000UL 131 #define BOARD_BOOTCLOCKRUN_MQS_CLK_ROOT 24000000UL 132 #define BOARD_BOOTCLOCKRUN_MQS_MCLK 24000000UL 133 #define BOARD_BOOTCLOCKRUN_OSC_24M 24000000UL 134 #define BOARD_BOOTCLOCKRUN_OSC_32K 32768UL 135 #define BOARD_BOOTCLOCKRUN_OSC_RC_16M 16000000UL 136 #define BOARD_BOOTCLOCKRUN_OSC_RC_400M 400000000UL 137 #define BOARD_BOOTCLOCKRUN_OSC_RC_48M 48000000UL 138 #define BOARD_BOOTCLOCKRUN_OSC_RC_48M_DIV2 24000000UL 139 #define BOARD_BOOTCLOCKRUN_PLL_AUDIO_CLK 0UL 140 #define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_MODULATION 0UL 141 #define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_RANGE 0UL 142 #define BOARD_BOOTCLOCKRUN_PLL_VIDEO_CLK 984000025UL 143 #define BOARD_BOOTCLOCKRUN_PLL_VIDEO_SS_MODULATION 0UL 144 #define BOARD_BOOTCLOCKRUN_PLL_VIDEO_SS_RANGE 0UL 145 #define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 24000000UL 146 #define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 24000000UL 147 #define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 0UL 148 #define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 24000000UL 149 #define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 24000000UL 150 #define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 24000000UL 151 #define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL 152 #define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 24000000UL 153 #define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 24000000UL 154 #define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 24000000UL 155 #define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL 156 #define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 24000000UL 157 #define BOARD_BOOTCLOCKRUN_SAI4_CLK_ROOT 24000000UL 158 #define BOARD_BOOTCLOCKRUN_SAI4_MCLK1 24000000UL 159 #define BOARD_BOOTCLOCKRUN_SAI4_MCLK2 0UL 160 #define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 198000000UL 161 #define BOARD_BOOTCLOCKRUN_SPDIF_CLK_ROOT 24000000UL 162 #define BOARD_BOOTCLOCKRUN_SPDIF_EXTCLK_OUT 0UL 163 #define BOARD_BOOTCLOCKRUN_SYS_PLL1_CLK 0UL 164 #define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV2_CLK 0UL 165 #define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV5_CLK 0UL 166 #define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_MODULATION 0UL 167 #define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_RANGE 0UL 168 #define BOARD_BOOTCLOCKRUN_SYS_PLL2_CLK 528000000UL 169 #define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD0_CLK 352000000UL 170 #define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD1_CLK 594000000UL 171 #define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD2_CLK 396000000UL 172 #define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD3_CLK 297000000UL 173 #define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_MODULATION 0UL 174 #define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_RANGE 0UL 175 #define BOARD_BOOTCLOCKRUN_SYS_PLL3_CLK 480000000UL 176 #define BOARD_BOOTCLOCKRUN_SYS_PLL3_DIV2_CLK 240000000UL 177 #define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD0_CLK 664615384UL 178 #define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD1_CLK 508235294UL 179 #define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD2_CLK 270000000UL 180 #define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD3_CLK 392727272UL 181 #define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 24000000UL 182 #define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 24000000UL 183 184 185 /******************************************************************************* 186 * API for BOARD_BootClockRUN configuration 187 ******************************************************************************/ 188 #if defined(__cplusplus) 189 extern "C" { 190 #endif /* __cplusplus*/ 191 192 /*! 193 * @brief This function executes configuration of clocks. 194 * 195 */ 196 void BOARD_BootClockRUN(void); 197 198 #if defined(__cplusplus) 199 } 200 #endif /* __cplusplus*/ 201 202 #endif /* _CLOCK_CONFIG_H_ */ 203 204