1 /*
2 * Copyright 2020-2021 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 /***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13 /*
14 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
15 !!GlobalInfo
16 product: Pins v9.0
17 processor: MIMXRT1176xxxxx
18 package_id: MIMXRT1176DVMAA
19 mcu_data: ksdk2_0
20 processor_version: 0.9.6
21 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
22 */
23
24 #include "fsl_common.h"
25 #include "fsl_iomuxc.h"
26 #include "fsl_gpio.h"
27 #include "pin_mux.h"
28
29 /* FUNCTION ************************************************************************************************************
30 *
31 * Function Name : BOARD_InitBootPins
32 * Description : Calls initialization functions.
33 *
34 * END ****************************************************************************************************************/
BOARD_InitBootPins(void)35 void BOARD_InitBootPins(void) {
36 BOARD_InitPins();
37 }
38
39 /*
40 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
41 BOARD_InitPins:
42 - options: {callFromInitBoot: 'true', coreID: cm7, enableClock: 'true'}
43 - pin_list:
44 - {pin_num: M15, peripheral: LPUART1, signal: RXD, pin_signal: GPIO_AD_25, software_input_on: Disable, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper,
45 open_drain: Disable, drive_strength: High, slew_rate: Slow}
46 - {pin_num: L13, peripheral: LPUART1, signal: TXD, pin_signal: GPIO_AD_24, software_input_on: Disable, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper,
47 open_drain: Disable, drive_strength: High, slew_rate: Slow}
48 - {pin_num: D6, peripheral: ARM, signal: arm_trace_swo, pin_signal: GPIO_DISP_B2_07, software_input_on: Disable, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper,
49 open_drain: Disable, drive_strength: High, slew_rate: Slow}
50 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
51 */
52
53 /* FUNCTION ************************************************************************************************************
54 *
55 * Function Name : BOARD_InitPins, assigned for the Cortex-M7F core.
56 * Description : Configures pin routing and optionally pin electrical features.
57 *
58 * END ****************************************************************************************************************/
BOARD_InitPins(void)59 void BOARD_InitPins(void) {
60 CLOCK_EnableClock(kCLOCK_Iomuxc); /* LPCG on: LPCG is ON. */
61 CLOCK_EnableClock(kCLOCK_Iomuxc_Lpsr); /* LPCG on: LPCG is ON. */
62
63 /* GPIO configuration on GPIO_AD_04 (pin M13) */
64 gpio_pin_config_t gpio9_pinM13_config = {
65 .direction = kGPIO_DigitalOutput,
66 .outputLogic = 0U,
67 .interruptMode = kGPIO_NoIntmode
68 };
69 /* Initialize GPIO functionality on GPIO_AD_04 (pin M13) */
70 GPIO_PinInit(GPIO9, 3U, &gpio9_pinM13_config);
71
72 /* GPIO configuration on GPIO_AD_26 (pin L14) */
73 gpio_pin_config_t gpio9_pinL14_config = {
74 .direction = kGPIO_DigitalOutput,
75 .outputLogic = 0U,
76 .interruptMode = kGPIO_NoIntmode
77 };
78 /* Initialize GPIO functionality on GPIO_AD_04 (pin L14) */
79 GPIO_PinInit(GPIO9, 25U, &gpio9_pinL14_config);
80
81 IOMUXC_SetPinMux(
82 IOMUXC_GPIO_AD_04_GPIO9_IO03, /* GPIO_AD_04 is configured as GPIO9_IO03 */
83 0U);
84 IOMUXC_SetPinMux(
85 IOMUXC_GPIO_AD_26_GPIO9_IO25, /* GPIO_AD_04 is configured as GPIO9_IO03 */
86 0U);
87 IOMUXC_SetPinMux(
88 IOMUXC_GPIO_AD_24_LPUART1_TXD, /* GPIO_AD_24 is configured as LPUART1_TXD */
89 0U); /* Software Input On Field: Input Path is determined by functionality */
90 IOMUXC_SetPinMux(
91 IOMUXC_GPIO_AD_25_LPUART1_RXD, /* GPIO_AD_25 is configured as LPUART1_RXD */
92 0U); /* Software Input On Field: Input Path is determined by functionality */
93 IOMUXC_SetPinMux(
94 IOMUXC_GPIO_DISP_B2_07_ARM_TRACE_SWO, /* GPIO_DISP_B2_07 is configured as ARM_TRACE_SWO */
95 0U); /* Software Input On Field: Input Path is determined by functionality */
96 IOMUXC_SetPinConfig(
97 IOMUXC_GPIO_AD_24_LPUART1_TXD, /* GPIO_AD_24 PAD functional properties : */
98 0x02U); /* Slew Rate Field: Slow Slew Rate
99 Drive Strength Field: high drive strength
100 Pull / Keep Select Field: Pull Disable, Highz
101 Pull Up / Down Config. Field: Weak pull down
102 Open Drain Field: Disabled
103 Domain write protection: Both cores are allowed
104 Domain write protection lock: Neither of DWP bits is locked */
105 IOMUXC_SetPinConfig(
106 IOMUXC_GPIO_AD_25_LPUART1_RXD, /* GPIO_AD_25 PAD functional properties : */
107 0x02U); /* Slew Rate Field: Slow Slew Rate
108 Drive Strength Field: high drive strength
109 Pull / Keep Select Field: Pull Disable, Highz
110 Pull Up / Down Config. Field: Weak pull down
111 Open Drain Field: Disabled
112 Domain write protection: Both cores are allowed
113 Domain write protection lock: Neither of DWP bits is locked */
114 IOMUXC_SetPinConfig(
115 IOMUXC_GPIO_DISP_B2_07_ARM_TRACE_SWO, /* GPIO_DISP_B2_07 PAD functional properties : */
116 0x02U); /* Slew Rate Field: Slow Slew Rate
117 Drive Strength Field: high drive strength
118 Pull / Keep Select Field: Pull Disable, Highz
119 Pull Up / Down Config. Field: Weak pull down
120 Open Drain Field: Disabled
121 Domain write protection: Both cores are allowed
122 Domain write protection lock: Neither of DWP bits is locked */
123 }
124
125 /***********************************************************************************************************************
126 * EOF
127 **********************************************************************************************************************/
128