1#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m7 -E -x c
2/*
3** ###################################################################
4**     Processors:          MIMXRT1176AVM8A_cm7
5**                          MIMXRT1176CVM8A_cm7
6**                          MIMXRT1176DVMAA_cm7
7**
8**     Compiler:            Keil ARM C/C++ Compiler
9**     Reference manual:    IMXRT1170RM, Rev E, 12/2019
10**     Version:             rev. 0.1, 2018-03-05
11**     Build:               b200828
12**
13**     Abstract:
14**         Linker file for the Keil ARM C/C++ Compiler
15**
16**     Copyright 2016 Freescale Semiconductor, Inc.
17**     Copyright 2016-2020 NXP
18**     All rights reserved.
19**
20**     SPDX-License-Identifier: BSD-3-Clause
21**
22**     http:                 www.nxp.com
23**     mail:                 support@nxp.com
24**
25** ###################################################################
26*/
27
28#if (defined(__ram_vector_table__))
29  #define __ram_vector_table_size__    0x00000400
30#else
31  #define __ram_vector_table_size__    0x00000000
32#endif
33
34#define m_flash_config_start           0x30000400
35#define m_flash_config_size            0x00000C00
36
37#define m_ivt_start                    0x30001000
38#define m_ivt_size                     0x00001000
39
40#define m_interrupts_start             0x30002000
41#define m_interrupts_size              0x00000400
42
43#define m_text_start                   0x30002400
44#define m_text_size                    0x00FFDC00
45
46#define m_interrupts_ram_start         0x80000000
47#define m_interrupts_ram_size          __ram_vector_table_size__
48
49#define  m_data_start                  (m_interrupts_ram_start + m_interrupts_ram_size)
50#define  m_data_size                   (0x03000000 - m_interrupts_ram_size)
51
52#define m_ncache_start                 0x83000000
53#define m_ncache_size                  0x01000000
54
55#define m_data2_start                  0x20000000
56#define m_data2_size                   0x00040000
57
58#define m_data3_start                  0x202C0000
59#define m_data3_size                   0x00080000
60
61/* Sizes */
62#if (defined(__stack_size__))
63  #define Stack_Size                   __stack_size__
64#else
65  #define Stack_Size                   0x0400
66#endif
67
68#if (defined(__heap_size__))
69  #define Heap_Size                    __heap_size__
70#else
71  #define Heap_Size                    0x0400
72#endif
73#include "../../rtconfig.h"
74#define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK))
75
76#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
77LR_m_text m_flash_config_start m_text_start+m_text_size-m_flash_config_start {   ; load region size_region
78  RW_m_config_text m_flash_config_start FIXED m_flash_config_size { ; load address = execution address
79    * (.boot_hdr.conf, +FIRST)
80  }
81
82  RW_m_ivt_text m_ivt_start FIXED m_ivt_size { ; load address = execution address
83    * (.boot_hdr.ivt, +FIRST)
84    * (.boot_hdr.boot_data)
85    * (.boot_hdr.dcd_data)
86  }
87#else
88LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start {   ; load region size_region
89#endif
90  VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
91    * (.isr_vector,+FIRST)
92  }
93  ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
94    * (InRoot$$Sections)
95    .ANY (+RO)
96  }
97#if (defined(__ram_vector_table__))
98  VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size {
99  }
100#else
101  VECTOR_RAM m_interrupts_start EMPTY 0 {
102  }
103#endif
104  RW_m_data2 m_data2_start m_data2_size {
105    * (RamFunction)
106  }
107#if (defined(__heap_noncacheable__))
108  RW_m_data m_data_start m_data_size-Stack_Size { ; RW data
109#else
110  RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
111#endif
112    .ANY (+RW +ZI)
113    *(*m_usb_dma_init_data)
114    *(*m_usb_dma_noninit_data)
115  }
116#if (!defined(__heap_noncacheable__))
117  ARM_LIB_HEAP +0 EMPTY Heap_Size {    ; Heap region growing up
118  }
119#endif
120 ; ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
121 ; }
122    ARM_LIB_STACK +0 EMPTY Stack_Size{} ; Stack region growing down
123    RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{}
124#if (defined(__heap_noncacheable__))
125  RW_m_ncache m_ncache_start m_ncache_size - Heap_Size { ; ncache RW data
126#else
127  RW_m_ncache m_ncache_start m_ncache_size { ; ncache RW data
128#endif
129    * (NonCacheable.init)
130    * (*NonCacheable)
131  }
132#if (defined(__heap_noncacheable__))
133  ARM_LIB_HEAP +0 EMPTY Heap_Size {    ; Heap region growing up
134  }
135  RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache)-Heap_Size { ; Empty region added for MPU configuration
136#else
137  RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration
138#endif
139  }
140}
141