1 /*
2 * Copyright (c) 2006-2023, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2018-4-30 misonyo the first version.
9 * 2022-6-22 solar Implement api docking of rt_pin_get.
10 */
11
12 #include <rtthread.h>
13 #ifdef BSP_USING_GPIO
14
15 #include <rthw.h>
16 #include "drv_gpio.h"
17 #include "board.h"
18 #include "fsl_gpio.h"
19 #include "fsl_iomuxc.h"
20
21 #define LOG_TAG "drv.gpio"
22 #include <drv_log.h>
23
24 #define IMX_PIN_NUM(port, no) (((((port) & 0x5u) << 5) | ((no) & 0x1Fu)))
25
26 #if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL
27 #error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!"
28 #endif
29
30 #define __IMXRT_HDR_DEFAULT {-1, 0, RT_NULL, RT_NULL}
31
32 #ifdef SOC_IMXRT1170_SERIES
33 #define PIN_INVALID_CHECK(PORT_INDEX, PIN_NUM) (PORT_INDEX > 7) || ((mask_tab[PORT_INDEX].valid_mask & (1 << PIN_NUM)) == 0)
34 #else
35 #define PIN_INVALID_CHECK(PORT_INDEX, PIN_NUM) (PORT_INDEX > 4) || ((mask_tab[PORT_INDEX].valid_mask & (1 << PIN_NUM)) == 0)
36 #endif
37
38 #if defined(SOC_IMXRT1015_SERIES)
39 #define MUX_BASE 0x401f8024
40 #define CONFIG_BASE 0x401f8198
41 #elif defined(SOC_IMXRT1020_SERIES)
42 #define MUX_BASE 0x401f8014
43 #define CONFIG_BASE 0x401f8188
44 #elif defined(SOC_IMXRT1170_SERIES)
45 #define MUX_BASE 0x400E8010
46 #define CONFIG_BASE 0x400E8254
47 #else /* 1050 & 1060 & 1064 series*/
48 #define MUX_BASE 0x401f8014
49 #define CONFIG_BASE 0x401f8204
50 #endif
51
52 #define GPIO5_MUX_BASE 0x400A8000
53 #define GPIO5_CONFIG_BASE 0x400A8018
54 #define GPIO6_MUX_BASE 0x40C08000
55 #define GPIO6_CONFIG_BASE 0x40C08040
56 #define GPIO13_MUX_BASE 0x40C94000
57 #define GPIO13_CONFIG_BASE 0x40C94040
58
59 struct pin_mask
60 {
61 GPIO_Type *gpio;
62 rt_int32_t valid_mask;
63 };
64
65 const struct pin_mask mask_tab[7] =
66 {
67 #if defined(SOC_IMXRT1015_SERIES)
68 {GPIO1, 0xfc00ffff}, /* GPIO1,16~25 not supported */
69 {GPIO2, 0xffff03f8}, /* GPIO2,0~2,10~15 not supported */
70 {GPIO3, 0x7ff0000f}, /* GPIO3,4~19 not supported */
71 {GPIO4, 0x00000000}, /* GPIO4 not supported */
72 {GPIO5, 0x00000001} /* GPIO5,0,2,3~31 not supported */
73 #elif defined(SOC_IMXRT1020_SERIES)
74 {GPIO1, 0xffffffff}, /* GPIO1 */
75 {GPIO2, 0xffffffff}, /* GPIO2 */
76 {GPIO3, 0xffffe3ff}, /* GPIO3,10~12 not supported */
77 {GPIO5, 0x00000000}, /* GPIO4 not supported */
78 {GPIO5, 0x00000007} /* GPIO5,3~31 not supported */
79 #elif defined(SOC_IMXRT1170_SERIES)
80 {GPIO1, 0xffffffff},
81 {GPIO2, 0xffffffff},
82 {GPIO3, 0xffffffff},
83 {GPIO4, 0xffffffff},
84 {GPIO5, 0x0001ffff},
85 {GPIO6, 0x0000ffff},
86 {GPIO13, 0x00001fff},
87 #else /* 1050 & 1060 & 1064 series*/
88 {GPIO1, 0xffffffff}, /* GPIO1 */
89 {GPIO2, 0xffffffff}, /* GPIO2 */
90 {GPIO3, 0x0fffffff}, /* GPIO3,28~31 not supported */
91 {GPIO4, 0xffffffff}, /* GPIO4 */
92 {GPIO5, 0x00000007} /* GPIO5,3~31 not supported */
93 #endif
94
95 };
96
97 const rt_int32_t reg_offset[] =
98 {
99 #if defined(SOC_IMXRT1015_SERIES)
100 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 64, 65, 66, 67, 68, 69,
101 -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, -1, -1, -1, -1, -1, -1, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, -1, -1, -1, -1,
102 28, 29, 30, 31, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88,
103 #elif defined(SOC_IMXRT1020_SERIES)
104 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73,
105 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
106 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, -1, -1, -1, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92,
107 #elif defined(SOC_IMXRT1170_SERIES)
108 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
109 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
110 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95,
111 96, 97, 98, 99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,
112 128,129, 130,131,132,133,134,135,136,137,138,139,140,141,142,143,144, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
113 #else /* 1050 & 1060 & 1064 series*/
114 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73,
115 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99,100,101,102,103,104,105,
116 112,113,114,115,116,117,118,119,120,121,122,123,106,107,108,109,110,111, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, -1, -1, -1, -1,
117 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
118 #endif
119
120 };
121
122 static const IRQn_Type irq_tab[13] =
123 {
124 GPIO1_Combined_0_15_IRQn,
125 GPIO1_Combined_16_31_IRQn,
126 GPIO2_Combined_0_15_IRQn,
127 GPIO2_Combined_16_31_IRQn,
128 GPIO3_Combined_0_15_IRQn,
129 GPIO3_Combined_16_31_IRQn,
130 #if !defined(SOC_IMXRT1020_SERIES)
131 GPIO4_Combined_0_15_IRQn,
132 GPIO4_Combined_16_31_IRQn,
133 #endif
134 GPIO5_Combined_0_15_IRQn,
135 GPIO5_Combined_16_31_IRQn,
136 #if defined(SOC_IMXRT1170_SERIES)
137 GPIO6_Combined_0_15_IRQn,
138 GPIO6_Combined_16_31_IRQn,
139 GPIO13_Combined_0_31_IRQn
140 #endif
141 };
142
143 static struct rt_pin_irq_hdr hdr_tab[] =
144 {
145 /* GPIO1 */
146 __IMXRT_HDR_DEFAULT,
147 __IMXRT_HDR_DEFAULT,
148 __IMXRT_HDR_DEFAULT,
149 __IMXRT_HDR_DEFAULT,
150 __IMXRT_HDR_DEFAULT,
151 __IMXRT_HDR_DEFAULT,
152 __IMXRT_HDR_DEFAULT,
153 __IMXRT_HDR_DEFAULT,
154 __IMXRT_HDR_DEFAULT,
155 __IMXRT_HDR_DEFAULT,
156 __IMXRT_HDR_DEFAULT,
157 __IMXRT_HDR_DEFAULT,
158 __IMXRT_HDR_DEFAULT,
159 __IMXRT_HDR_DEFAULT,
160 __IMXRT_HDR_DEFAULT,
161 __IMXRT_HDR_DEFAULT,
162 __IMXRT_HDR_DEFAULT,
163 __IMXRT_HDR_DEFAULT,
164 __IMXRT_HDR_DEFAULT,
165 __IMXRT_HDR_DEFAULT,
166 __IMXRT_HDR_DEFAULT,
167 __IMXRT_HDR_DEFAULT,
168 __IMXRT_HDR_DEFAULT,
169 __IMXRT_HDR_DEFAULT,
170 __IMXRT_HDR_DEFAULT,
171 __IMXRT_HDR_DEFAULT,
172 __IMXRT_HDR_DEFAULT,
173 __IMXRT_HDR_DEFAULT,
174 __IMXRT_HDR_DEFAULT,
175 __IMXRT_HDR_DEFAULT,
176 __IMXRT_HDR_DEFAULT,
177 __IMXRT_HDR_DEFAULT,
178 /* GPIO2 */
179 __IMXRT_HDR_DEFAULT,
180 __IMXRT_HDR_DEFAULT,
181 __IMXRT_HDR_DEFAULT,
182 __IMXRT_HDR_DEFAULT,
183 __IMXRT_HDR_DEFAULT,
184 __IMXRT_HDR_DEFAULT,
185 __IMXRT_HDR_DEFAULT,
186 __IMXRT_HDR_DEFAULT,
187 __IMXRT_HDR_DEFAULT,
188 __IMXRT_HDR_DEFAULT,
189 __IMXRT_HDR_DEFAULT,
190 __IMXRT_HDR_DEFAULT,
191 __IMXRT_HDR_DEFAULT,
192 __IMXRT_HDR_DEFAULT,
193 __IMXRT_HDR_DEFAULT,
194 __IMXRT_HDR_DEFAULT,
195 __IMXRT_HDR_DEFAULT,
196 __IMXRT_HDR_DEFAULT,
197 __IMXRT_HDR_DEFAULT,
198 __IMXRT_HDR_DEFAULT,
199 __IMXRT_HDR_DEFAULT,
200 __IMXRT_HDR_DEFAULT,
201 __IMXRT_HDR_DEFAULT,
202 __IMXRT_HDR_DEFAULT,
203 __IMXRT_HDR_DEFAULT,
204 __IMXRT_HDR_DEFAULT,
205 __IMXRT_HDR_DEFAULT,
206 __IMXRT_HDR_DEFAULT,
207 __IMXRT_HDR_DEFAULT,
208 __IMXRT_HDR_DEFAULT,
209 __IMXRT_HDR_DEFAULT,
210 __IMXRT_HDR_DEFAULT,
211 /* GPIO3 */
212 __IMXRT_HDR_DEFAULT,
213 __IMXRT_HDR_DEFAULT,
214 __IMXRT_HDR_DEFAULT,
215 __IMXRT_HDR_DEFAULT,
216 __IMXRT_HDR_DEFAULT,
217 __IMXRT_HDR_DEFAULT,
218 __IMXRT_HDR_DEFAULT,
219 __IMXRT_HDR_DEFAULT,
220 __IMXRT_HDR_DEFAULT,
221 __IMXRT_HDR_DEFAULT,
222 __IMXRT_HDR_DEFAULT,
223 __IMXRT_HDR_DEFAULT,
224 __IMXRT_HDR_DEFAULT,
225 __IMXRT_HDR_DEFAULT,
226 __IMXRT_HDR_DEFAULT,
227 __IMXRT_HDR_DEFAULT,
228 __IMXRT_HDR_DEFAULT,
229 __IMXRT_HDR_DEFAULT,
230 __IMXRT_HDR_DEFAULT,
231 __IMXRT_HDR_DEFAULT,
232 __IMXRT_HDR_DEFAULT,
233 __IMXRT_HDR_DEFAULT,
234 __IMXRT_HDR_DEFAULT,
235 __IMXRT_HDR_DEFAULT,
236 __IMXRT_HDR_DEFAULT,
237 __IMXRT_HDR_DEFAULT,
238 __IMXRT_HDR_DEFAULT,
239 __IMXRT_HDR_DEFAULT,
240 __IMXRT_HDR_DEFAULT,
241 __IMXRT_HDR_DEFAULT,
242 __IMXRT_HDR_DEFAULT,
243 __IMXRT_HDR_DEFAULT,
244 /* GPIO4 */
245 __IMXRT_HDR_DEFAULT,
246 __IMXRT_HDR_DEFAULT,
247 __IMXRT_HDR_DEFAULT,
248 __IMXRT_HDR_DEFAULT,
249 __IMXRT_HDR_DEFAULT,
250 __IMXRT_HDR_DEFAULT,
251 __IMXRT_HDR_DEFAULT,
252 __IMXRT_HDR_DEFAULT,
253 __IMXRT_HDR_DEFAULT,
254 __IMXRT_HDR_DEFAULT,
255 __IMXRT_HDR_DEFAULT,
256 __IMXRT_HDR_DEFAULT,
257 __IMXRT_HDR_DEFAULT,
258 __IMXRT_HDR_DEFAULT,
259 __IMXRT_HDR_DEFAULT,
260 __IMXRT_HDR_DEFAULT,
261 __IMXRT_HDR_DEFAULT,
262 __IMXRT_HDR_DEFAULT,
263 __IMXRT_HDR_DEFAULT,
264 __IMXRT_HDR_DEFAULT,
265 __IMXRT_HDR_DEFAULT,
266 __IMXRT_HDR_DEFAULT,
267 __IMXRT_HDR_DEFAULT,
268 __IMXRT_HDR_DEFAULT,
269 __IMXRT_HDR_DEFAULT,
270 __IMXRT_HDR_DEFAULT,
271 __IMXRT_HDR_DEFAULT,
272 __IMXRT_HDR_DEFAULT,
273 __IMXRT_HDR_DEFAULT,
274 __IMXRT_HDR_DEFAULT,
275 __IMXRT_HDR_DEFAULT,
276 __IMXRT_HDR_DEFAULT,
277 /* GPIO5 */
278 __IMXRT_HDR_DEFAULT,
279 __IMXRT_HDR_DEFAULT,
280 __IMXRT_HDR_DEFAULT,
281 __IMXRT_HDR_DEFAULT,
282 __IMXRT_HDR_DEFAULT,
283 __IMXRT_HDR_DEFAULT,
284 __IMXRT_HDR_DEFAULT,
285 __IMXRT_HDR_DEFAULT,
286 __IMXRT_HDR_DEFAULT,
287 __IMXRT_HDR_DEFAULT,
288 __IMXRT_HDR_DEFAULT,
289 __IMXRT_HDR_DEFAULT,
290 __IMXRT_HDR_DEFAULT,
291 __IMXRT_HDR_DEFAULT,
292 __IMXRT_HDR_DEFAULT,
293 __IMXRT_HDR_DEFAULT,
294 __IMXRT_HDR_DEFAULT,
295 __IMXRT_HDR_DEFAULT,
296 __IMXRT_HDR_DEFAULT,
297 __IMXRT_HDR_DEFAULT,
298 __IMXRT_HDR_DEFAULT,
299 __IMXRT_HDR_DEFAULT,
300 __IMXRT_HDR_DEFAULT,
301 __IMXRT_HDR_DEFAULT,
302 __IMXRT_HDR_DEFAULT,
303 __IMXRT_HDR_DEFAULT,
304 __IMXRT_HDR_DEFAULT,
305 __IMXRT_HDR_DEFAULT,
306 __IMXRT_HDR_DEFAULT,
307 __IMXRT_HDR_DEFAULT,
308 __IMXRT_HDR_DEFAULT,
309 __IMXRT_HDR_DEFAULT,
310 /* GPIO6 */
311 #if defined(SOC_IMXRT1170_SERIES)
312 __IMXRT_HDR_DEFAULT,
313 __IMXRT_HDR_DEFAULT,
314 __IMXRT_HDR_DEFAULT,
315 __IMXRT_HDR_DEFAULT,
316 __IMXRT_HDR_DEFAULT,
317 __IMXRT_HDR_DEFAULT,
318 __IMXRT_HDR_DEFAULT,
319 __IMXRT_HDR_DEFAULT,
320 __IMXRT_HDR_DEFAULT,
321 __IMXRT_HDR_DEFAULT,
322 __IMXRT_HDR_DEFAULT,
323 __IMXRT_HDR_DEFAULT,
324 __IMXRT_HDR_DEFAULT,
325 __IMXRT_HDR_DEFAULT,
326 __IMXRT_HDR_DEFAULT,
327 __IMXRT_HDR_DEFAULT,
328 __IMXRT_HDR_DEFAULT,
329 __IMXRT_HDR_DEFAULT,
330 __IMXRT_HDR_DEFAULT,
331 __IMXRT_HDR_DEFAULT,
332 __IMXRT_HDR_DEFAULT,
333 __IMXRT_HDR_DEFAULT,
334 __IMXRT_HDR_DEFAULT,
335 __IMXRT_HDR_DEFAULT,
336 __IMXRT_HDR_DEFAULT,
337 __IMXRT_HDR_DEFAULT,
338 __IMXRT_HDR_DEFAULT,
339 __IMXRT_HDR_DEFAULT,
340 __IMXRT_HDR_DEFAULT,
341 __IMXRT_HDR_DEFAULT,
342 __IMXRT_HDR_DEFAULT,
343 __IMXRT_HDR_DEFAULT,
344 /* GPIO13 */
345 __IMXRT_HDR_DEFAULT,
346 __IMXRT_HDR_DEFAULT,
347 __IMXRT_HDR_DEFAULT,
348 __IMXRT_HDR_DEFAULT,
349 __IMXRT_HDR_DEFAULT,
350 __IMXRT_HDR_DEFAULT,
351 __IMXRT_HDR_DEFAULT,
352 __IMXRT_HDR_DEFAULT,
353 __IMXRT_HDR_DEFAULT,
354 __IMXRT_HDR_DEFAULT,
355 __IMXRT_HDR_DEFAULT,
356 __IMXRT_HDR_DEFAULT,
357 __IMXRT_HDR_DEFAULT,
358 __IMXRT_HDR_DEFAULT,
359 __IMXRT_HDR_DEFAULT,
360 __IMXRT_HDR_DEFAULT,
361 __IMXRT_HDR_DEFAULT,
362 __IMXRT_HDR_DEFAULT,
363 __IMXRT_HDR_DEFAULT,
364 __IMXRT_HDR_DEFAULT,
365 __IMXRT_HDR_DEFAULT,
366 __IMXRT_HDR_DEFAULT,
367 __IMXRT_HDR_DEFAULT,
368 __IMXRT_HDR_DEFAULT,
369 __IMXRT_HDR_DEFAULT,
370 __IMXRT_HDR_DEFAULT,
371 __IMXRT_HDR_DEFAULT,
372 __IMXRT_HDR_DEFAULT,
373 __IMXRT_HDR_DEFAULT,
374 __IMXRT_HDR_DEFAULT,
375 __IMXRT_HDR_DEFAULT,
376 __IMXRT_HDR_DEFAULT,
377 #endif
378 };
379
imxrt_isr(rt_int16_t index_offset,rt_int8_t pin_start,GPIO_Type * base)380 static void imxrt_isr(rt_int16_t index_offset, rt_int8_t pin_start, GPIO_Type *base)
381 {
382 rt_int32_t isr_status, index;
383 rt_int8_t i, pin_end;
384
385 pin_end = pin_start + 15;
386 isr_status = GPIO_PortGetInterruptFlags(base) & base->IMR;
387
388 for (i = pin_start; i <= pin_end ; i++)
389 {
390 if (isr_status & (1 << i))
391 {
392 GPIO_PortClearInterruptFlags(base, (1 << i));
393 index = index_offset + i;
394 if (hdr_tab[index].hdr != RT_NULL)
395 {
396 hdr_tab[index].hdr(hdr_tab[index].args);
397 }
398 }
399 }
400 }
401
402 /* GPIO1 index offset is 0 */
GPIO1_Combined_0_15_IRQHandler(void)403 void GPIO1_Combined_0_15_IRQHandler(void)
404 {
405 rt_interrupt_enter();
406
407 imxrt_isr(0, 0, GPIO1);
408
409 rt_interrupt_leave();
410 }
411
GPIO1_Combined_16_31_IRQHandler(void)412 void GPIO1_Combined_16_31_IRQHandler(void)
413 {
414 rt_interrupt_enter();
415
416 imxrt_isr(0, 16, GPIO1);
417
418 rt_interrupt_leave();
419 }
420
421 /* GPIO2 index offset is 32 */
GPIO2_Combined_0_15_IRQHandler(void)422 void GPIO2_Combined_0_15_IRQHandler(void)
423 {
424 rt_interrupt_enter();
425
426 imxrt_isr(32, 0, GPIO2);
427
428 rt_interrupt_leave();
429 }
430
GPIO2_Combined_16_31_IRQHandler(void)431 void GPIO2_Combined_16_31_IRQHandler(void)
432 {
433 rt_interrupt_enter();
434
435 imxrt_isr(32, 16, GPIO2);
436
437 rt_interrupt_leave();
438 }
439
440 /* GPIO3 index offset is 64 */
GPIO3_Combined_0_15_IRQHandler(void)441 void GPIO3_Combined_0_15_IRQHandler(void)
442 {
443 rt_interrupt_enter();
444
445 imxrt_isr(64, 0, GPIO3);
446
447 rt_interrupt_leave();
448 }
449
GPIO3_Combined_16_31_IRQHandler(void)450 void GPIO3_Combined_16_31_IRQHandler(void)
451 {
452 rt_interrupt_enter();
453
454 imxrt_isr(64, 16, GPIO3);
455
456 rt_interrupt_leave();
457 }
458
459 #ifdef GPIO4
460 /* GPIO4 index offset is 96 */
GPIO4_Combined_0_15_IRQHandler(void)461 void GPIO4_Combined_0_15_IRQHandler(void)
462 {
463 rt_interrupt_enter();
464
465 imxrt_isr(96, 0, GPIO4);
466
467 rt_interrupt_leave();
468 }
GPIO4_Combined_16_31_IRQHandler(void)469 void GPIO4_Combined_16_31_IRQHandler(void)
470 {
471 rt_interrupt_enter();
472
473 imxrt_isr(96, 16, GPIO4);
474
475 rt_interrupt_leave();
476 }
477 #endif
478
479 /* GPIO5 index offset is 128 */
GPIO5_Combined_0_15_IRQHandler(void)480 void GPIO5_Combined_0_15_IRQHandler(void)
481 {
482 rt_interrupt_enter();
483
484 imxrt_isr(128, 0, GPIO5);
485
486 rt_interrupt_leave();
487 }
GPIO5_Combined_16_31_IRQHandler(void)488 void GPIO5_Combined_16_31_IRQHandler(void)
489 {
490 rt_interrupt_enter();
491
492 imxrt_isr(128, 16, GPIO5);
493
494 rt_interrupt_leave();
495 }
496 #if defined(SOC_IMXRT1170_SERIES)
GPIO6_Combined_0_15_IRQHandler(void)497 void GPIO6_Combined_0_15_IRQHandler(void)
498 {
499 rt_interrupt_enter();
500
501 imxrt_isr(160, 0, GPIO6);
502
503 rt_interrupt_leave();
504 }
GPIO6_Combined_16_31_IRQHandler(void)505 void GPIO6_Combined_16_31_IRQHandler(void)
506 {
507 rt_interrupt_enter();
508
509 imxrt_isr(160, 16, GPIO6);
510
511 rt_interrupt_leave();
512 }
GPIO13_Combined_0_31_IRQHandler(void)513 void GPIO13_Combined_0_31_IRQHandler(void)
514 {
515 rt_interrupt_enter();
516
517 imxrt_isr(192, 0, GPIO13);
518 imxrt_isr(192, 16, GPIO13);
519 rt_interrupt_leave();
520 }
521 #endif
imxrt_pin_mode(rt_device_t dev,rt_base_t pin,rt_uint8_t mode)522 static void imxrt_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
523 {
524 gpio_pin_config_t gpio;
525 rt_int8_t port, pin_num;
526
527 #ifndef SOC_IMXRT1170_SERIES
528 rt_uint32_t config_value = 0;
529 #endif
530
531 port = pin >> 5;
532 pin_num = pin & 31;
533
534 if (PIN_INVALID_CHECK(port, pin_num))
535 {
536 LOG_D("invalid pin,rtt pin: %d,port: %d,pin: %d \n", pin,port + 1,pin_num);
537 return;
538 }
539
540 gpio.outputLogic = 0;
541 gpio.interruptMode = kGPIO_NoIntmode;
542
543 switch (mode)
544 {
545 case PIN_MODE_OUTPUT:
546 {
547 gpio.direction = kGPIO_DigitalOutput;
548 #ifndef SOC_IMXRT1170_SERIES
549 config_value = 0x0030U; /* Drive Strength R0/6 */
550 #endif
551 }
552 break;
553
554 case PIN_MODE_INPUT:
555 {
556 gpio.direction = kGPIO_DigitalInput;
557 #ifndef SOC_IMXRT1170_SERIES
558 config_value = 0x0830U; /* Open Drain Enable */
559 #endif
560 }
561 break;
562
563 case PIN_MODE_INPUT_PULLDOWN:
564 {
565 gpio.direction = kGPIO_DigitalInput;
566 #ifndef SOC_IMXRT1170_SERIES
567 config_value = 0x3030U; /* 100K Ohm Pull Down */
568 #endif
569 }
570 break;
571
572 case PIN_MODE_INPUT_PULLUP:
573 {
574 gpio.direction = kGPIO_DigitalInput;
575 #ifndef SOC_IMXRT1170_SERIES
576 config_value = 0xB030U; /* 100K Ohm Pull Up */
577 #endif
578 }
579 break;
580
581 case PIN_MODE_OUTPUT_OD:
582 {
583 gpio.direction = kGPIO_DigitalOutput;
584 #ifndef SOC_IMXRT1170_SERIES
585 config_value = 0x0830U; /* Open Drain Enable */
586 #endif
587 }
588 break;
589 }
590 #ifndef SOC_IMXRT1170_SERIES
591 if (mask_tab[port].gpio != GPIO5)
592 {
593 CLOCK_EnableClock(kCLOCK_Iomuxc);
594 IOMUXC_SetPinMux(MUX_BASE + reg_offset[pin] * 4, 0x5U, 0, 0, CONFIG_BASE + reg_offset[pin] * 4, 1);
595 IOMUXC_SetPinConfig(MUX_BASE + reg_offset[pin] * 4, 0x5U, 0, 0, CONFIG_BASE + reg_offset[pin] * 4, config_value);
596 }
597 else
598 {
599 CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
600 IOMUXC_SetPinMux(GPIO5_MUX_BASE + pin_num * 4, 0x5U, 0, 0, GPIO5_CONFIG_BASE + pin_num * 4, 1);
601 IOMUXC_SetPinConfig(GPIO5_MUX_BASE + pin_num * 4, 0x5U, 0, 0, GPIO5_CONFIG_BASE + pin_num * 4, config_value);
602 }
603 #else
604 if ((mask_tab[port].gpio != GPIO6) && (mask_tab[port].gpio != GPIO13))
605 {
606 CLOCK_EnableClock(kCLOCK_Iomuxc);
607 IOMUXC_SetPinMux(MUX_BASE + reg_offset[pin] * 4, 0x5U, 0, 0, CONFIG_BASE + reg_offset[pin] * 4, 1);
608 }
609 if (mask_tab[port].gpio == GPIO6)
610 {
611 CLOCK_EnableClock(kCLOCK_Iomuxc_Lpsr);
612 IOMUXC_SetPinMux(GPIO6_MUX_BASE + pin_num * 4, 0x5U, 0, 0, GPIO6_CONFIG_BASE + pin_num * 4, 1);
613 }
614 if (mask_tab[port].gpio == GPIO13)
615 {
616 CLOCK_EnableClock(kCLOCK_Iomuxc);
617 IOMUXC_SetPinMux(GPIO13_MUX_BASE + pin_num * 4, 0x5U, 0, 0, GPIO13_CONFIG_BASE + pin_num * 4, 1);
618 }
619
620 #endif
621
622 GPIO_PinInit(mask_tab[port].gpio, pin_num, &gpio);
623 }
624
imxrt_pin_read(rt_device_t dev,rt_base_t pin)625 static rt_ssize_t imxrt_pin_read(rt_device_t dev, rt_base_t pin)
626 {
627 rt_ssize_t value;
628 rt_int8_t port, pin_num;
629
630 value = PIN_LOW;
631 port = pin >> 5;
632 pin_num = pin & 31;
633
634 if (PIN_INVALID_CHECK(port, pin_num))
635 {
636 LOG_D("invalid pin,rtt pin: %d,port: %d,pin: %d \n", pin,port + 1,pin_num);
637 return -RT_EINVAL;
638 }
639
640 return GPIO_PinReadPadStatus(mask_tab[port].gpio, pin_num);
641 }
642
imxrt_pin_write(rt_device_t dev,rt_base_t pin,rt_uint8_t value)643 static void imxrt_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
644 {
645 rt_int8_t port, pin_num;
646
647 port = pin >> 5;
648 pin_num = pin & 31;
649
650 if (PIN_INVALID_CHECK(port, pin_num))
651 {
652 LOG_D("invalid pin,rtt pin: %d,port: %d,pin: %d \n", pin,port + 1,pin_num);
653 return;
654 }
655
656 GPIO_PinWrite(mask_tab[port].gpio, pin_num, value);
657 }
658
imxrt_pin_attach_irq(struct rt_device * device,rt_base_t pin,rt_uint8_t mode,void (* hdr)(void * args),void * args)659 static rt_err_t imxrt_pin_attach_irq(struct rt_device *device, rt_base_t pin,
660 rt_uint8_t mode, void (*hdr)(void *args), void *args)
661 {
662 rt_base_t level;
663 rt_int8_t port, pin_num;
664
665 port = pin >> 5;
666 pin_num = pin & 31;
667
668 if (PIN_INVALID_CHECK(port, pin_num))
669 {
670 LOG_D("invalid pin,rtt pin: %d,port: %d,pin: %d \n", pin,port + 1,pin_num);
671 return -RT_ENOSYS;
672 }
673
674 level = rt_hw_interrupt_disable();
675 if (hdr_tab[pin].pin == pin &&
676 hdr_tab[pin].hdr == hdr &&
677 hdr_tab[pin].mode == mode &&
678 hdr_tab[pin].args == args)
679 {
680 rt_hw_interrupt_enable(level);
681 return RT_EOK;
682 }
683
684 hdr_tab[pin].pin = pin;
685 hdr_tab[pin].hdr = hdr;
686 hdr_tab[pin].mode = mode;
687 hdr_tab[pin].args = args;
688 rt_hw_interrupt_enable(level);
689
690 return RT_EOK;
691 }
692
imxrt_pin_detach_irq(struct rt_device * device,rt_base_t pin)693 static rt_err_t imxrt_pin_detach_irq(struct rt_device *device, rt_base_t pin)
694 {
695 rt_base_t level;
696 rt_int8_t port, pin_num;
697
698 port = pin >> 5;
699 pin_num = pin & 31;
700
701 if (PIN_INVALID_CHECK(port, pin_num))
702 {
703 LOG_D("invalid pin,rtt pin: %d,port: %d,pin: %d \n", pin,port + 1,pin_num);
704 return -RT_ENOSYS;
705 }
706
707 level = rt_hw_interrupt_disable();
708 if (hdr_tab[pin].pin == -1)
709 {
710 rt_hw_interrupt_enable(level);
711 return RT_EOK;
712 }
713 hdr_tab[pin].pin = -1;
714 hdr_tab[pin].hdr = RT_NULL;
715 hdr_tab[pin].mode = 0;
716 hdr_tab[pin].args = RT_NULL;
717 rt_hw_interrupt_enable(level);
718
719 return RT_EOK;
720 }
721
imxrt_pin_irq_enable(struct rt_device * device,rt_base_t pin,rt_uint8_t enabled)722 static rt_err_t imxrt_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled)
723 {
724 gpio_interrupt_mode_t int_mode;
725 rt_int8_t port, pin_num, irq_index;
726
727 port = pin >> 5;
728 pin_num = pin & 31;
729
730 if (PIN_INVALID_CHECK(port, pin_num))
731 {
732 LOG_D("invalid pin,rtt pin: %d,port: %d,pin: %d \n", pin,port + 1,pin_num);
733 return -RT_ENOSYS;
734 }
735
736 if (hdr_tab[pin].pin == -1)
737 {
738 LOG_D("rtt pin: %d callback function not initialized!\n", pin);
739 return -RT_ENOSYS;
740 }
741
742 if (enabled == PIN_IRQ_ENABLE)
743 {
744 switch (hdr_tab[pin].mode)
745 {
746 case PIN_IRQ_MODE_RISING:
747 int_mode = kGPIO_IntRisingEdge;
748 break;
749 case PIN_IRQ_MODE_FALLING:
750 int_mode = kGPIO_IntFallingEdge;
751 break;
752 case PIN_IRQ_MODE_RISING_FALLING:
753 int_mode = kGPIO_IntRisingOrFallingEdge;
754 break;
755 case PIN_IRQ_MODE_HIGH_LEVEL:
756 int_mode = kGPIO_IntHighLevel;
757 break;
758 case PIN_IRQ_MODE_LOW_LEVEL:
759 int_mode = kGPIO_IntLowLevel;
760 break;
761 default:
762 int_mode = kGPIO_IntRisingEdge;
763 break;
764 }
765 irq_index = (port << 1) + (pin_num >> 4);
766 GPIO_PinSetInterruptConfig(mask_tab[port].gpio, pin_num, int_mode);
767 GPIO_PortEnableInterrupts(mask_tab[port].gpio, 1U << pin_num);
768 NVIC_SetPriority(irq_tab[irq_index], NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 5, 0));
769 EnableIRQ(irq_tab[irq_index]);
770 }
771 else if (enabled == PIN_IRQ_DISABLE)
772 {
773 GPIO_PortDisableInterrupts(mask_tab[port].gpio, 1U << pin_num);
774 }
775 else
776 {
777 return -RT_EINVAL;
778 }
779
780 return RT_EOK;
781 }
782
783 /* Example of use: Px.0 ~ Px.31, x:1,2,3,4,5 */
imxrt_pin_get(const char * name)784 static rt_base_t imxrt_pin_get(const char *name)
785 {
786 rt_base_t pin = 0;
787 int hw_port_num, hw_pin_num = 0;
788 int i, name_len;
789
790 name_len = rt_strlen(name);
791
792 if ((name_len < 4) || (name_len >= 6))
793 {
794 return -RT_EINVAL;
795 }
796 if ((name[0] != 'P') || (name[2] != '.'))
797 {
798 return -RT_EINVAL;
799 }
800
801 if ((name[1] >= '1') && (name[1] <= '5'))
802 {
803 hw_port_num = (int)(name[1] - '1');
804 }
805 else
806 {
807 return -RT_EINVAL;
808 }
809
810 for (i = 3; i < name_len; i++)
811 {
812 hw_pin_num *= 10;
813 hw_pin_num += name[i] - '0';
814 }
815
816 pin = IMX_PIN_NUM(hw_port_num, hw_pin_num);
817
818 return pin;
819 }
820
821 const static struct rt_pin_ops imxrt_pin_ops =
822 {
823 imxrt_pin_mode,
824 imxrt_pin_write,
825 imxrt_pin_read,
826 imxrt_pin_attach_irq,
827 imxrt_pin_detach_irq,
828 imxrt_pin_irq_enable,
829 imxrt_pin_get,
830 };
831
rt_hw_pin_init(void)832 int rt_hw_pin_init(void)
833 {
834 int ret = RT_EOK;
835
836 ret = rt_device_pin_register("pin", &imxrt_pin_ops, RT_NULL);
837
838 return ret;
839 }
840 INIT_BOARD_EXPORT(rt_hw_pin_init);
841
842 #endif /* BSP_USING_GPIO */
843