1 /*
2 * Copyright (c) 2006-2021, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 */
9 #include <rtthread.h>
10 #include "emac.h"
11 #include "lwipopts.h"
12 #include <netif/ethernetif.h>
13
14 #define EMAC_PHY_AUTO 0
15 #define EMAC_PHY_10MBIT 1
16 #define EMAC_PHY_100MBIT 2
17
18 #define MAX_ADDR_LEN 6
19 struct lpc17xx_emac
20 {
21 /* inherit from ethernet device */
22 struct eth_device parent;
23
24 rt_uint8_t phy_mode;
25
26 /* interface address info. */
27 rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */
28 };
29 static struct lpc17xx_emac lpc17xx_emac_device;
30 static struct rt_semaphore sem_lock;
31 static struct rt_event tx_event;
32
33 /* Local Function Prototypes */
34 static void write_PHY (rt_uint32_t PhyReg, rt_uint32_t Value);
35 static rt_uint16_t read_PHY (rt_uint8_t PhyReg) ;
36
ENET_IRQHandler(void)37 void ENET_IRQHandler(void)
38 {
39 rt_uint32_t status;
40
41 /* enter interrupt */
42 rt_interrupt_enter();
43
44 status = LPC_EMAC->IntStatus;
45
46 if (status & INT_RX_DONE)
47 {
48 /* Disable EMAC RxDone interrupts. */
49 LPC_EMAC->IntEnable = INT_TX_DONE;
50
51 /* a frame has been received */
52 eth_device_ready(&(lpc17xx_emac_device.parent));
53 }
54 else if (status & INT_TX_DONE)
55 {
56 /* set event */
57 rt_event_send(&tx_event, 0x01);
58 }
59
60 if (status & INT_RX_OVERRUN)
61 {
62 rt_kprintf("rx overrun\n");
63 }
64
65 if (status & INT_TX_UNDERRUN)
66 {
67 rt_kprintf("tx underrun\n");
68 }
69
70 /* Clear the interrupt. */
71 LPC_EMAC->IntClear = status;
72
73 /* leave interrupt */
74 rt_interrupt_leave();
75 }
76
77 /* phy write */
write_PHY(rt_uint32_t PhyReg,rt_uint32_t Value)78 static void write_PHY (rt_uint32_t PhyReg, rt_uint32_t Value)
79 {
80 unsigned int tout;
81
82 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
83 LPC_EMAC->MWTD = Value;
84
85 /* Wait utill operation completed */
86 tout = 0;
87 for (tout = 0; tout < MII_WR_TOUT; tout++)
88 {
89 if ((LPC_EMAC->MIND & MIND_BUSY) == 0)
90 {
91 break;
92 }
93 }
94 }
95
96 /* phy read */
read_PHY(rt_uint8_t PhyReg)97 static rt_uint16_t read_PHY (rt_uint8_t PhyReg)
98 {
99 rt_uint32_t tout;
100
101 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
102 LPC_EMAC->MCMD = MCMD_READ;
103
104 /* Wait until operation completed */
105 tout = 0;
106 for (tout = 0; tout < MII_RD_TOUT; tout++)
107 {
108 if ((LPC_EMAC->MIND & MIND_BUSY) == 0)
109 {
110 break;
111 }
112 }
113 LPC_EMAC->MCMD = 0;
114 return (LPC_EMAC->MRDD);
115 }
116
117 /* init rx descriptor */
rx_descr_init(void)118 rt_inline void rx_descr_init (void)
119 {
120 rt_uint32_t i;
121
122 for (i = 0; i < NUM_RX_FRAG; i++)
123 {
124 RX_DESC_PACKET(i) = RX_BUF(i);
125 RX_DESC_CTRL(i) = RCTRL_INT | (ETH_FRAG_SIZE-1);
126 RX_STAT_INFO(i) = 0;
127 RX_STAT_HASHCRC(i) = 0;
128 }
129
130 /* Set EMAC Receive Descriptor Registers. */
131 LPC_EMAC->RxDescriptor = RX_DESC_BASE;
132 LPC_EMAC->RxStatus = RX_STAT_BASE;
133 LPC_EMAC->RxDescriptorNumber = NUM_RX_FRAG-1;
134
135 /* Rx Descriptors Point to 0 */
136 LPC_EMAC->RxConsumeIndex = 0;
137 }
138
139 /* init tx descriptor */
tx_descr_init(void)140 rt_inline void tx_descr_init (void)
141 {
142 rt_uint32_t i;
143
144 for (i = 0; i < NUM_TX_FRAG; i++)
145 {
146 TX_DESC_PACKET(i) = TX_BUF(i);
147 TX_DESC_CTRL(i) = (1ul<<31) | (1ul<<30) | (1ul<<29) | (1ul<<28) | (1ul<<26) | (ETH_FRAG_SIZE-1);
148 TX_STAT_INFO(i) = 0;
149 }
150
151 /* Set EMAC Transmit Descriptor Registers. */
152 LPC_EMAC->TxDescriptor = TX_DESC_BASE;
153 LPC_EMAC->TxStatus = TX_STAT_BASE;
154 LPC_EMAC->TxDescriptorNumber = NUM_TX_FRAG-1;
155
156 /* Tx Descriptors Point to 0 */
157 LPC_EMAC->TxProduceIndex = 0;
158 }
159
lpc17xx_emac_init(rt_device_t dev)160 static rt_err_t lpc17xx_emac_init(rt_device_t dev)
161 {
162 /* Initialize the EMAC ethernet controller. */
163 rt_uint32_t regv, tout, id1, id2;
164
165 /* Power Up the EMAC controller. */
166 LPC_SC->PCONP |= 0x40000000;
167
168 /* Enable P1 Ethernet Pins. */
169 LPC_PINCON->PINSEL2 = 0x50150105;
170 LPC_PINCON->PINSEL3 = (LPC_PINCON->PINSEL3 & ~0x0000000F) | 0x00000005;
171
172 /* Reset all EMAC internal modules. */
173 LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX |
174 MAC1_SIM_RES | MAC1_SOFT_RES;
175 LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES;
176
177 /* A short delay after reset. */
178 for (tout = 100; tout; tout--);
179
180 /* Initialize MAC control registers. */
181 LPC_EMAC->MAC1 = MAC1_PASS_ALL;
182 LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
183 LPC_EMAC->MAXF = ETH_MAX_FLEN;
184 LPC_EMAC->CLRT = CLRT_DEF;
185 LPC_EMAC->IPGR = IPGR_DEF;
186
187 /* PCLK=18MHz, clock select=6, MDC=18/6=3MHz */
188 /* Enable Reduced MII interface. */
189 LPC_EMAC->MCFG = MCFG_CLK_DIV20 | MCFG_RES_MII;
190 for (tout = 100; tout; tout--);
191 LPC_EMAC->MCFG = MCFG_CLK_DIV20;
192
193 /* Enable Reduced MII interface. */
194 LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM | CR_PASS_RX_FILT;
195
196 /* Reset Reduced MII Logic. */
197 LPC_EMAC->SUPP = SUPP_RES_RMII | SUPP_SPEED;
198 for (tout = 100; tout; tout--);
199 LPC_EMAC->SUPP = SUPP_SPEED;
200
201 /* Put the PHY in reset mode */
202 write_PHY (PHY_REG_BMCR, 0x8000);
203 for (tout = 1000; tout; tout--);
204
205 /* Wait for hardware reset to end. */
206 for (tout = 0; tout < 10000; tout++)
207 {
208 regv = read_PHY (PHY_REG_BMCR);
209 if (!(regv & 0x8000))
210 {
211 /* Reset complete */
212 break;
213 }
214 }
215 if (tout >= 10000)
216 {
217 //return -RT_ERROR; /* reset failed */
218 rt_kprintf("\tPHY Read PHY_REG_BMSR,Reset timeout,tout: %d.\n",tout);
219 }
220
221 /* Check if this is a DP83848C PHY. */
222 id1 = read_PHY (PHY_REG_IDR1);
223 id2 = read_PHY (PHY_REG_IDR2);
224
225 if (((id1 << 16) | (id2 & 0xFFF0)) != DP83848C_ID)
226 {
227 // return -RT_ERROR;
228 rt_kprintf("\tPHY Read PHY_REG_IDRx,PHY chip isn't DP83848C,Chip ID is %d.\n",((id1 << 16) | (id2 & 0xFFF0)));
229 }
230 else
231 {
232 /* Configure the PHY device */
233 /* Configure the PHY device */
234 switch (lpc17xx_emac_device.phy_mode)
235 {
236 case EMAC_PHY_AUTO:
237 /* Use auto negotiation about the link speed. */
238 write_PHY (PHY_REG_BMCR, PHY_AUTO_NEG);
239 /* Wait to complete Auto_Negotiation. */
240 for (tout = 0; tout < 200000; tout++)
241 {
242 regv = read_PHY (PHY_REG_BMSR);
243 if (regv & 0x0020)
244 {
245 /* Auto negotiation Complete. */
246 break;
247 }
248 }
249 if(tout >= 200000)
250 {
251 rt_kprintf("\tPHY Read PHY_REG_BMSR,Auto nego timeout,tout: %d.\n",tout);
252 }
253 break;
254 case EMAC_PHY_10MBIT:
255 /* Connect at 10MBit */
256 write_PHY (PHY_REG_BMCR, PHY_FULLD_10M);
257 break;
258 case EMAC_PHY_100MBIT:
259 /* Connect at 100MBit */
260 write_PHY (PHY_REG_BMCR, PHY_FULLD_100M);
261 break;
262 }
263 }
264 //if (tout >= 0x100000) return -RT_ERROR; // auto_neg failed
265
266 /* Check the link status. */
267 for (tout = 0; tout < 100; tout++)
268 {
269 regv = read_PHY (PHY_REG_STS);
270 if (regv & 0x0001)
271 {
272 /* Link is on. */
273 break;
274 }
275 }
276 if (tout >= 100)
277 {
278 //return -RT_ERROR;
279 rt_kprintf("\tPHY Read PHY_REG_BMSR,Link on timeout,tout: %d.\n",tout);
280 }
281 /* Configure Full/Half Duplex mode. */
282 if (regv & 0x0004)
283 {
284 /* Full duplex is enabled. */
285 LPC_EMAC->MAC2 |= MAC2_FULL_DUP;
286 LPC_EMAC->Command |= CR_FULL_DUP;
287 LPC_EMAC->IPGT = IPGT_FULL_DUP;
288 }
289 else
290 {
291 /* Half duplex mode. */
292 LPC_EMAC->IPGT = IPGT_HALF_DUP;
293 }
294
295 /* Configure 100MBit/10MBit mode. */
296 if (regv & 0x0002)
297 {
298 /* 10MBit mode. */
299 LPC_EMAC->SUPP = 0;
300 }
301 else
302 {
303 /* 100MBit mode. */
304 LPC_EMAC->SUPP = SUPP_SPEED;
305 }
306
307 /* Set the Ethernet MAC Address registers */
308 LPC_EMAC->SA0 = (lpc17xx_emac_device.dev_addr[1]<<8) | lpc17xx_emac_device.dev_addr[0];
309 LPC_EMAC->SA1 = (lpc17xx_emac_device.dev_addr[3]<<8) | lpc17xx_emac_device.dev_addr[2];
310 LPC_EMAC->SA2 = (lpc17xx_emac_device.dev_addr[5]<<8) | lpc17xx_emac_device.dev_addr[4];
311
312 /* Initialize Tx and Rx DMA Descriptors */
313 rx_descr_init ();
314 tx_descr_init ();
315
316 /* Receive Broadcast and Perfect Match Packets */
317 LPC_EMAC->RxFilterCtrl = RFC_BCAST_EN | RFC_PERFECT_EN;
318
319 /* Reset all interrupts */
320 LPC_EMAC->IntClear = 0xFFFF;
321
322 /* Enable EMAC interrupts. */
323 LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE;
324
325 /* Enable receive and transmit mode of MAC Ethernet core */
326 LPC_EMAC->Command |= (CR_RX_EN | CR_TX_EN);
327 LPC_EMAC->MAC1 |= MAC1_REC_EN;
328
329 /* Enable the ENET Interrupt */
330 NVIC_EnableIRQ(ENET_IRQn);
331
332 return RT_EOK;
333 }
334
lpc17xx_emac_open(rt_device_t dev,rt_uint16_t oflag)335 static rt_err_t lpc17xx_emac_open(rt_device_t dev, rt_uint16_t oflag)
336 {
337 return RT_EOK;
338 }
339
lpc17xx_emac_close(rt_device_t dev)340 static rt_err_t lpc17xx_emac_close(rt_device_t dev)
341 {
342 return RT_EOK;
343 }
344
lpc17xx_emac_read(rt_device_t dev,rt_off_t pos,void * buffer,rt_size_t size)345 static rt_ssize_t lpc17xx_emac_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
346 {
347 return -RT_ENOSYS;
348 }
349
lpc17xx_emac_write(rt_device_t dev,rt_off_t pos,const void * buffer,rt_size_t size)350 static rt_ssize_t lpc17xx_emac_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
351 {
352 return -RT_ENOSYS;
353 }
354
lpc17xx_emac_control(rt_device_t dev,int cmd,void * args)355 static rt_err_t lpc17xx_emac_control(rt_device_t dev, int cmd, void *args)
356 {
357 switch (cmd)
358 {
359 case NIOCTL_GADDR:
360 /* get mac address */
361 if (args) rt_memcpy(args, lpc17xx_emac_device.dev_addr, 6);
362 else return -RT_ERROR;
363 break;
364
365 default :
366 break;
367 }
368
369 return RT_EOK;
370 }
371
372 /* EtherNet Device Interface */
373 /* transmit packet. */
lpc17xx_emac_tx(rt_device_t dev,struct pbuf * p)374 rt_err_t lpc17xx_emac_tx( rt_device_t dev, struct pbuf* p)
375 {
376 rt_uint32_t Index, IndexNext;
377 struct pbuf *q;
378 rt_uint8_t *ptr;
379
380 /* calculate next index */
381 IndexNext = LPC_EMAC->TxProduceIndex + 1;
382 if(IndexNext > LPC_EMAC->TxDescriptorNumber) IndexNext = 0;
383
384 /* check whether block is full */
385 while (IndexNext == LPC_EMAC->TxConsumeIndex)
386 {
387 rt_err_t result;
388 rt_uint32_t recved;
389
390 /* there is no block yet, wait a flag */
391 result = rt_event_recv(&tx_event, 0x01,
392 RT_EVENT_FLAG_AND | RT_EVENT_FLAG_CLEAR, RT_WAITING_FOREVER, &recved);
393
394 RT_ASSERT(result == RT_EOK);
395 }
396
397 /* lock EMAC device */
398 rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
399
400 /* get produce index */
401 Index = LPC_EMAC->TxProduceIndex;
402
403 /* calculate next index */
404 IndexNext = LPC_EMAC->TxProduceIndex + 1;
405 if(IndexNext > LPC_EMAC->TxDescriptorNumber)
406 IndexNext = 0;
407
408 /* copy data to tx buffer */
409 q = p;
410 ptr = (rt_uint8_t*)TX_BUF(Index);
411 while (q)
412 {
413 memcpy(ptr, q->payload, q->len);
414 ptr += q->len;
415 q = q->next;
416 }
417
418 TX_DESC_CTRL(Index) &= ~0x7ff;
419 TX_DESC_CTRL(Index) |= (p->tot_len - 1) & 0x7ff;
420
421 /* change index to the next */
422 LPC_EMAC->TxProduceIndex = IndexNext;
423
424 /* unlock EMAC device */
425 rt_sem_release(&sem_lock);
426
427 return RT_EOK;
428 }
429
430 /* reception packet. */
lpc17xx_emac_rx(rt_device_t dev)431 struct pbuf *lpc17xx_emac_rx(rt_device_t dev)
432 {
433 struct pbuf* p;
434 rt_uint32_t size;
435 rt_uint32_t Index;
436
437 /* init p pointer */
438 p = RT_NULL;
439
440 /* lock EMAC device */
441 rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
442
443 Index = LPC_EMAC->RxConsumeIndex;
444 if(Index != LPC_EMAC->RxProduceIndex)
445 {
446 size = (RX_STAT_INFO(Index) & 0x7ff)+1;
447 if (size > ETH_FRAG_SIZE) size = ETH_FRAG_SIZE;
448
449 /* allocate buffer */
450 p = pbuf_alloc(PBUF_LINK, size, PBUF_RAM);
451 if (p != RT_NULL)
452 {
453 struct pbuf* q;
454 rt_uint8_t *ptr;
455
456 ptr = (rt_uint8_t*)RX_BUF(Index);
457 for (q = p; q != RT_NULL; q= q->next)
458 {
459 memcpy(q->payload, ptr, q->len);
460 ptr += q->len;
461 }
462 }
463
464 /* move Index to the next */
465 if(++Index > LPC_EMAC->RxDescriptorNumber)
466 Index = 0;
467
468 /* set consume index */
469 LPC_EMAC->RxConsumeIndex = Index;
470 }
471 else
472 {
473 /* Enable RxDone interrupt */
474 LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE;
475 }
476
477 /* unlock EMAC device */
478 rt_sem_release(&sem_lock);
479
480 return p;
481 }
482
lpc17xx_emac_hw_init(void)483 int lpc17xx_emac_hw_init(void)
484 {
485 rt_event_init(&tx_event, "tx_event", RT_IPC_FLAG_FIFO);
486 rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
487
488 /* set auto negotiation mode */
489 lpc17xx_emac_device.phy_mode = EMAC_PHY_AUTO;
490
491 // OUI 00-60-37 NXP Semiconductors
492 lpc17xx_emac_device.dev_addr[0] = 0x00;
493 lpc17xx_emac_device.dev_addr[1] = 0x60;
494 lpc17xx_emac_device.dev_addr[2] = 0x37;
495 /* set mac address: (only for test) */
496 lpc17xx_emac_device.dev_addr[3] = 0x12;
497 lpc17xx_emac_device.dev_addr[4] = 0x34;
498 lpc17xx_emac_device.dev_addr[5] = 0x56;
499
500 lpc17xx_emac_device.parent.parent.init = lpc17xx_emac_init;
501 lpc17xx_emac_device.parent.parent.open = lpc17xx_emac_open;
502 lpc17xx_emac_device.parent.parent.close = lpc17xx_emac_close;
503 lpc17xx_emac_device.parent.parent.read = lpc17xx_emac_read;
504 lpc17xx_emac_device.parent.parent.write = lpc17xx_emac_write;
505 lpc17xx_emac_device.parent.parent.control = lpc17xx_emac_control;
506 lpc17xx_emac_device.parent.parent.user_data = RT_NULL;
507
508 lpc17xx_emac_device.parent.eth_rx = lpc17xx_emac_rx;
509 lpc17xx_emac_device.parent.eth_tx = lpc17xx_emac_tx;
510
511 eth_device_init(&(lpc17xx_emac_device.parent), "e0");
512 return 0;
513 }
514 INIT_DEVICE_EXPORT(lpc17xx_emac_hw_init);
515