1 /**********************************************************************
2 * $Id$ lpc177x_8x_emc.c 2011-06-02
3 *//**
4 * @file lpc177x_8x_emc.c
5 * @brief Contains all functions support for EMC firmware library
6 * on LPC177x_8x
7 * @version 1.0
8 * @date 02. June. 2011
9 * @author NXP MCU SW Application Team
10 *
11 * Copyright(C) 2011, NXP Semiconductor
12 * All rights reserved.
13 *
14 ***********************************************************************
15 * Software that is described herein is for illustrative purposes only
16 * which provides customers with programming information regarding the
17 * products. This software is supplied "AS IS" without any warranties.
18 * NXP Semiconductors assumes no responsibility or liability for the
19 * use of the software, conveys no license or title under any patent,
20 * copyright, or mask work right to the product. NXP Semiconductors
21 * reserves the right to make changes in the software without
22 * notification. NXP Semiconductors also make no representation or
23 * warranty that such application will be suitable for the specified
24 * use without further testing or modification.
25 **********************************************************************/
26
27 #include "lpc177x_8x_emc.h"
28 #include "lpc177x_8x_clkpwr.h"
29 #include "lpc177x_8x_pinsel.h"
30
31
32 /*********************************************************************//**
33 * @brief EMC initialize
34 * @param[in] None
35 * @return None
36 **********************************************************************/
EMC_Init(void)37 void EMC_Init(void)
38 {
39 uint8_t i;
40
41 /* Enable clock for EMC */
42 // CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCEMC, ENABLE);
43 // LPC_EMC->Control = 0x00000001;
44 // LPC_EMC->Config = 0x00000000;
45
46 LPC_SC->PCONP |= 0x00000800;
47 LPC_SC->EMCDLYCTL = 0x00001010;
48 LPC_EMC->Control = 0x00000001;
49 LPC_EMC->Config = 0x00000000;
50
51 /* Pin configuration:
52 * P2.14 - /EMC_CS2
53 * P2.15 - /EMC_CS3
54 *
55 * P2.16 - /EMC_CAS
56 * P2.17 - /EMC_RAS
57 * P2.18 - EMC_CLK[0]
58 * P2.19 - EMC_CLK[1]
59 *
60 * P2.20 - EMC_DYCS0
61 * P2.22 - EMC_DYCS1
62 * P2.22 - EMC_DYCS2
63 * P2.23 - EMC_DYCS3
64 *
65 * P2.24 - EMC_CKE0
66 * P2.25 - EMC_CKE1
67 * P2.26 - EMC_CKE2
68 * P2.27 - EMC_CKE3
69 *
70 * P2.28 - EMC_DQM0
71 * P2.29 - EMC_DQM1
72 * P2.30 - EMC_DQM2
73 * P2.31 - EMC_DQM3
74 *
75 * P3.0-P3.31 - EMC_D[0-31]
76 * P4.0-P4.23 - EMC_A[0-23]
77 *
78 * P4.24 - /EMC_OE
79 * P4.25 - /EMC_WE
80 *
81 * P4.30 - /EMC_CS0
82 * P4.31 - /EMC_CS1
83 */
84 PINSEL_ConfigPin(2,14,1);
85 PINSEL_ConfigPin(2,15,1);
86 PINSEL_ConfigPin(2,16,1);
87 PINSEL_ConfigPin(2,17,1);
88 PINSEL_ConfigPin(2,18,1);
89 PINSEL_ConfigPin(2,19,1);
90 PINSEL_ConfigPin(2,20,1);
91 PINSEL_ConfigPin(2,21,1);
92 PINSEL_ConfigPin(2,22,1);
93 PINSEL_ConfigPin(2,23,1);
94 PINSEL_ConfigPin(2,24,1);
95 PINSEL_ConfigPin(2,25,1);
96 PINSEL_ConfigPin(2,26,1);
97 PINSEL_ConfigPin(2,27,1);
98 PINSEL_ConfigPin(2,28,1);
99 PINSEL_ConfigPin(2,29,1);
100 PINSEL_ConfigPin(2,30,1);
101 PINSEL_ConfigPin(2,31,1);
102
103 PINSEL_ConfigPin(5,0,1);
104 PINSEL_ConfigPin(5,1,1);
105
106 for(i = 0; i < 32; i++)
107 {
108 PINSEL_ConfigPin(3,i,1);
109 PINSEL_ConfigPin(4,i,1);
110 }
111 }
112 /*********************************************************************//**
113 * @brief Configure Little Endian/Big Endian mode for EMC
114 * @param[in] endia_mode Endian mode, should be:
115 * - EMC_LITTLE_ENDIAN_MODE: Little-endian mode
116 * - EMC_BIG_ENDIAN_MODE : Big-endian mode
117 * @return None
118 **********************************************************************/
EMC_ConfigEndianMode(uint32_t endian_mode)119 void EMC_ConfigEndianMode(uint32_t endian_mode)
120 {
121 LPC_EMC->Config = ((LPC_EMC->Config & 0x01)|endian_mode) & EMC_Config_MASK;
122 }
123
124 /****************** Group of Dynamic control functions************************/
125 /*********************************************************************//**
126 * @brief Set the value for dynamic clock enable bit
127 * @param[in] clock_enable clock enable mode, should be:
128 * - 0: Clock enable of idle devices are deasserted to
129 * save power
130 * - 1: All clock enables are driven HIGH continuously
131 * @return None
132 **********************************************************************/
EMC_DynCtrlClockEnable(uint32_t clock_enable)133 void EMC_DynCtrlClockEnable(uint32_t clock_enable)
134 {
135 LPC_EMC->DynamicControl = ((LPC_EMC->DynamicControl) |clock_enable);
136 }
137
138 /*********************************************************************//**
139 * @brief Set the value for dynamic memory clock control:
140 * stops or runs continuously
141 * @param[in] clock_control clock control mode, should be:
142 * - 0: CLKOUT stops when all SDRAMs are idle and
143 * during self-refresh mode
144 * - 1: CLKOUT runs continuously
145 * @return None
146 **********************************************************************/
EMC_DynCtrlClockControl(int32_t clock_control)147 void EMC_DynCtrlClockControl(int32_t clock_control)
148 {
149 uint32_t mask = ~(uint32_t)(2);
150 LPC_EMC->DynamicControl = ((LPC_EMC->DynamicControl & mask) |clock_control);
151 }
152
153 /*********************************************************************//**
154 * @brief Switch the Self-refresh mode between normal and self-refresh mode
155 * @param[in] self_refresh_mode self refresh mode, should be:
156 * - 0: Normal mode
157 * - 1: Enter self-refresh mode
158 * @return None
159 **********************************************************************/
EMC_DynCtrlSelfRefresh(uint32_t self_refresh_mode)160 void EMC_DynCtrlSelfRefresh(uint32_t self_refresh_mode)
161 {
162 uint32_t mask = ~(uint32_t)(4);
163 LPC_EMC->DynamicControl = ((LPC_EMC->DynamicControl & mask) |self_refresh_mode);
164 }
165
166 /*********************************************************************//**
167 * @brief Enable/disable CLKOUT
168 * @param[in] MMC_val Memory clock control mode, should be:
169 * - 0: CLKOUT enabled
170 * - 1: CLKOUT disabled
171 * @return None
172 **********************************************************************/
EMC_DynCtrlMMC(uint32_t MMC_val)173 void EMC_DynCtrlMMC(uint32_t MMC_val)
174 {
175 uint32_t mask = ~(uint32_t)(_BIT(5));
176 LPC_EMC->DynamicControl = ((LPC_EMC->DynamicControl & mask) |MMC_val);
177 }
178
179 /*********************************************************************//**
180 * @brief Issue SDRAM command
181 * @param[in] SDRAM_command Command mode, should be:
182 * - 0x00: Issue SDRAM NORMAL operation command
183 * - 0x01: Issue SDRAM MODE command
184 * - 0x02: Issue SDRAM PALL (precharge all) command
185 * - 0x03: Issue SRAM NOP (no operation) command
186 * @return None
187 **********************************************************************/
EMC_DynCtrlSDRAMInit(uint32_t SDRAM_command)188 void EMC_DynCtrlSDRAMInit(uint32_t SDRAM_command)
189 {
190 uint32_t mask = ~(uint32_t)(_SBF(7,0x03));
191 LPC_EMC->DynamicControl = ((LPC_EMC->DynamicControl & mask)|SDRAM_command);
192 }
193
194 /*********************************************************************//**
195 * @brief Switch between Normal operation and deep sleep power mode
196 * @param[in] Power_command Low-power SDRAM deep-sleep mode, should be:
197 * - 0: Normal operation
198 * - 1: Enter deep-sleep mode
199 * @return None
200 **********************************************************************/
EMC_DynCtrlPowerDownMode(uint32_t Power_command)201 void EMC_DynCtrlPowerDownMode(uint32_t Power_command)
202 {
203 uint32_t mask = ~(uint32_t)(_BIT(13));
204 LPC_EMC->DynamicControl = ((LPC_EMC->DynamicControl & mask)|Power_command);
205 }
206
207 /*********************************************************************//**
208 * @brief Set the value of EMC dynamic memory registers
209 * @param[in] par EMC register that will set value, should be:
210 * - EMC_DYN_MEM_REFRESH_TIMER: Dynamic Refresh register
211 * - EMC_DYN_MEM_READ_CONFIG: Dynamic Read Config register
212 * - EMC_DYN_MEM_TRP: Dynamic RP register
213 * - EMC_DYN_MEM_TRAS: Dynamic RAS register
214 * - EMC_DYN_MEM_TSREX: Dynamic SREX register
215 * - EMC_DYN_MEM_TAPR: Dynamic APR register
216 * - EMC_DYN_MEM_TDAL: Dynamic DAL register
217 * - EMC_DYN_MEM_TWR: Dynamic WR register
218 * - EMC_DYN_MEM_TRC: Dynamic RC register
219 * - EMC_DYN_MEM_TRFC: Dynamic RFC register
220 * - EMC_DYN_MEM_TXSR: Dynamic XSR register
221 * - EMC_DYN_MEM_TRRD: Dynamic RRD register
222 * - EMC_DYN_MEM_TMRD: Dynamic MRD register
223 * @return None
224 **********************************************************************/
EMC_SetDynMemoryParameter(EMC_DYN_MEM_PAR par,uint32_t val)225 void EMC_SetDynMemoryParameter(EMC_DYN_MEM_PAR par, uint32_t val)
226 {
227 switch ( par)
228 {
229 case EMC_DYN_MEM_REFRESH_TIMER:
230 LPC_EMC->DynamicRefresh = val;
231 break;
232 case EMC_DYN_MEM_READ_CONFIG:
233 LPC_EMC->DynamicReadConfig = val;
234 break;
235 case EMC_DYN_MEM_TRP:
236 LPC_EMC->DynamicRP = val;
237 break;
238 case EMC_DYN_MEM_TRAS:
239 LPC_EMC->DynamicRAS = val;
240 break;
241 case EMC_DYN_MEM_TSREX:
242 LPC_EMC->DynamicSREX = val;
243 break;
244 case EMC_DYN_MEM_TAPR:
245 LPC_EMC->DynamicAPR = val;
246 break;
247 case EMC_DYN_MEM_TDAL:
248 LPC_EMC->DynamicDAL = val;
249 break;
250 case EMC_DYN_MEM_TWR:
251 LPC_EMC->DynamicWR = val;
252 break;
253 case EMC_DYN_MEM_TRC:
254 LPC_EMC->DynamicRC = val;
255 break;
256 case EMC_DYN_MEM_TRFC:
257 LPC_EMC->DynamicRFC = val;
258 break;
259 case EMC_DYN_MEM_TXSR:
260 LPC_EMC->DynamicXSR = val;
261 break;
262 case EMC_DYN_MEM_TRRD:
263 LPC_EMC->DynamicRRD = val;
264 break;
265 case EMC_DYN_MEM_TMRD:
266 LPC_EMC->DynamicMRD = val;
267 break;
268 }
269 }
270
271 /*********************************************************************//**
272 * @brief Set extended wait time out for accessing static memory
273 * @param[in] Extended_wait_time_out timeout value that will be set
274 * @return None
275 **********************************************************************/
EMC_StaticExtendedWait(uint32_t Extended_wait_time_out)276 void EMC_StaticExtendedWait(uint32_t Extended_wait_time_out)
277 {
278 LPC_EMC->StaticExtendedWait = Extended_wait_time_out;
279 }
280
281 /*********************************************************************//**
282 * @brief Configure the memory device
283 * @param[in] index index number, should be from 0 to 3
284 * @param[in] mem_dev Memory device, should be:
285 * - 0x00: SDRAM
286 * - 0x01: Low-power SDRAM
287 * - 0x02: Micron Syncflash
288 * @return None
289 **********************************************************************/
EMC_DynMemConfigMD(uint32_t index,uint32_t mem_dev)290 void EMC_DynMemConfigMD(uint32_t index , uint32_t mem_dev)
291 {
292 uint32_t mask = ~(uint32_t)(_SBF(3, 0x03));
293 switch ( index)
294 {
295 case 0:
296 LPC_EMC->DynamicConfig0 = (LPC_EMC->DynamicConfig0 & mask) | mem_dev;
297 break;
298 case 1:
299 LPC_EMC->DynamicConfig1 = (LPC_EMC->DynamicConfig1 & mask) | mem_dev;
300 break;
301 case 2:
302 LPC_EMC->DynamicConfig2 =(LPC_EMC->DynamicConfig2 & mask) | mem_dev;
303 break;
304 case 3:
305 LPC_EMC->DynamicConfig3 = (LPC_EMC->DynamicConfig3 & mask) | mem_dev;
306 break;
307 }
308 }
309
310 /*********************************************************************//**
311 * @brief Map the address for the memory device
312 * @param[in] index index number, should be from 0 to 3
313 * @param[in] add_mapped address where the memory will be mapped
314 * @return None
315 **********************************************************************/
EMC_DynMemConfigAM(uint32_t index,uint32_t add_mapped)316 void EMC_DynMemConfigAM(uint32_t index , uint32_t add_mapped)
317 {
318 uint32_t mask = ~(uint32_t)(_SBF(7, 0x3f)) | ~(uint32_t)(_BIT(14)) ;
319
320 switch ( index)
321 {
322 case 0:
323 LPC_EMC->DynamicConfig0 = ( LPC_EMC->DynamicConfig0 & mask) | add_mapped;
324 break;
325 case 1:
326 LPC_EMC->DynamicConfig1 = (LPC_EMC->DynamicConfig1 & mask) | add_mapped;
327 break;
328 case 2:
329 LPC_EMC->DynamicConfig2 = (LPC_EMC->DynamicConfig2 & mask) | add_mapped;
330 break;
331 case 3:
332 LPC_EMC->DynamicConfig3 = (LPC_EMC->DynamicConfig3 & mask) | add_mapped;
333 break;
334 }
335 }
336
337 /*********************************************************************//**
338 * @brief Enable/disable the buffer
339 * @param[in] index index number, should be from 0 to 3
340 * @param[in] buff_control buffer control mode, should be:
341 * - ENABLE
342 * - DISABLE
343 * @return None
344 **********************************************************************/
EMC_DynMemConfigB(uint32_t index,uint32_t buff_control)345 void EMC_DynMemConfigB(uint32_t index , uint32_t buff_control)
346 {
347 uint32_t mask = ~(uint32_t)(_BIT(19)) ;
348 switch ( index)
349 {
350 case 0:
351 LPC_EMC->DynamicConfig0 = (LPC_EMC->DynamicConfig0 & mask) | buff_control;
352 break;
353 case 1:
354 LPC_EMC->DynamicConfig1 = ( LPC_EMC->DynamicConfig1 & mask) | buff_control;
355 break;
356 case 2:
357 LPC_EMC->DynamicConfig2 = (LPC_EMC->DynamicConfig2 & mask)| buff_control;
358 break;
359 case 3:
360 LPC_EMC->DynamicConfig3 = (LPC_EMC->DynamicConfig3 & mask) | buff_control;
361 break;
362 }
363 }
364
365
366 /*********************************************************************//**
367 * @brief Configure write permission: protect or not
368 * @param[in] index index number, should be from 0 to 3
369 * @param[in] permission permission mode, should be:
370 * - ENABLE: protect
371 * - DISABLE: not protect
372 * @return None
373 **********************************************************************/
EMC_DynMemConfigP(uint32_t index,uint32_t permission)374 void EMC_DynMemConfigP(uint32_t index , uint32_t permission)
375 {
376 uint32_t mask = ~(uint32_t)(_BIT(20)) ;
377 switch ( index)
378 {
379 case 0:
380 LPC_EMC->DynamicConfig0 = (LPC_EMC->DynamicConfig0 & mask) | permission;
381 break;
382 case 1:
383 LPC_EMC->DynamicConfig1 = (LPC_EMC->DynamicConfig1 & mask) | permission;
384 break;
385 case 2:
386 LPC_EMC->DynamicConfig2 = ( LPC_EMC->DynamicConfig2 & mask) | permission;
387 break;
388 case 3:
389 LPC_EMC->DynamicConfig3 = (LPC_EMC->DynamicConfig3 & mask) | permission;
390 break;
391 }
392 }
393
394 /*********************************************************************//**
395 * @brief Set value for RAS latency
396 * @param[in] index index number, should be from 0 to 3
397 * @param[in] ras_val RAS value should be in range: 0..3
398 * @return None
399 **********************************************************************/
EMC_DynMemRAS(uint32_t index,uint32_t ras_val)400 void EMC_DynMemRAS(uint32_t index , uint32_t ras_val)
401 {
402 uint32_t mask = ~(uint32_t)(0x03) ;
403
404 switch ( index)
405 {
406 case 0:
407 LPC_EMC->DynamicRasCas0 = (LPC_EMC->DynamicRasCas0 & mask) | ras_val;
408 break;
409 case 1:
410 LPC_EMC->DynamicRasCas1 = (LPC_EMC->DynamicRasCas1 & mask) | ras_val;
411 break;
412 case 2:
413 LPC_EMC->DynamicRasCas2 = (LPC_EMC->DynamicRasCas2 & mask) | ras_val;
414 break;
415 case 3:
416 LPC_EMC->DynamicRasCas3 = (LPC_EMC->DynamicRasCas3 & mask) | ras_val;
417 break;
418 }
419 }
420
421 /*********************************************************************//**
422 * @brief Set value for CAS latency
423 * @param[in] index index number, should be from 0 to 3
424 * @param[in] ras_val CAS value should be in range: 0..3
425 * @return None
426 **********************************************************************/
EMC_DynMemCAS(uint32_t index,uint32_t cas_val)427 void EMC_DynMemCAS(uint32_t index , uint32_t cas_val)
428 {
429 uint32_t mask = ~(uint32_t)(_SBF(8, 0x03)) ;
430 switch ( index)
431 {
432 case 0:
433 LPC_EMC->DynamicRasCas0 = (LPC_EMC->DynamicRasCas0 & mask) | cas_val;
434 break;
435 case 1:
436 LPC_EMC->DynamicRasCas1 = (LPC_EMC->DynamicRasCas1 & mask) | cas_val;
437 break;
438 case 2:
439 LPC_EMC->DynamicRasCas2 = (LPC_EMC->DynamicRasCas2 & mask )| cas_val;
440 break;
441 case 3:
442 LPC_EMC->DynamicRasCas3 = ( LPC_EMC->DynamicRasCas3 & mask) | cas_val;
443 break;
444 }
445 }
446 /*********************************************************************//**
447 * @brief Configure the memory width
448 * @param[in] index index number, should be from 0 to 3
449 * @param[in] mem_width memory width, should be:
450 * - 0x00: 8-bits
451 * - 0x01: 16-bits
452 * - 0x02: 32-bits
453 * @return None
454 **********************************************************************/
EMC_StaMemConfigMW(uint32_t index,uint32_t mem_width)455 void EMC_StaMemConfigMW(uint32_t index , uint32_t mem_width)
456 {
457 uint32_t mask = ~(uint32_t)(0x03) ;
458 switch ( index)
459 {
460 case 0:
461 LPC_EMC->StaticConfig0 = (LPC_EMC->StaticConfig0 & mask) | mem_width;
462 break;
463 case 1:
464 LPC_EMC->StaticConfig1 = (LPC_EMC->StaticConfig1 & mask) | mem_width;
465 break;
466 case 2:
467 LPC_EMC->StaticConfig2 = (LPC_EMC->StaticConfig2 & mask)| mem_width;
468 break;
469 case 3:
470 LPC_EMC->StaticConfig3 = (LPC_EMC->StaticConfig3 & mask) | mem_width;
471 break;
472 }
473 }
474 /*********************************************************************//**
475 * @brief Configure the page mode
476 * @param[in] index index number, should be from 0 to 3
477 * @param[in] page_mode page mode, should be:
478 * - 0: disable
479 * - 1: asynchronous page mode enable
480 * @return None
481 **********************************************************************/
EMC_StaMemConfigPM(uint32_t index,uint32_t page_mode)482 void EMC_StaMemConfigPM(uint32_t index , uint32_t page_mode)
483 {
484 uint32_t mask = ~(uint32_t)(_BIT(3)) ;
485 switch ( index)
486 {
487 case 0:
488 LPC_EMC->StaticConfig0 = (LPC_EMC->StaticConfig0 & mask) | page_mode;
489 break;
490 case 1:
491 LPC_EMC->StaticConfig1 = (LPC_EMC->StaticConfig1 & mask) | page_mode;
492 break;
493 case 2:
494 LPC_EMC->StaticConfig2 = (LPC_EMC->StaticConfig2 & mask)| page_mode;
495 break;
496 case 3:
497 LPC_EMC->StaticConfig3 = (LPC_EMC->StaticConfig3 & mask)| page_mode;
498 break;
499 }
500 }
501 /*********************************************************************//**
502 * @brief Configure the chip select polarity
503 * @param[in] index index number, should be from 0 to 3
504 * @param[in] pagepol_val_mode page mode, should be:
505 * - 0: Active LOW ship select
506 * - 1: Active HIGH chip select
507 * @return None
508 **********************************************************************/
EMC_StaMemConfigPC(uint32_t index,uint32_t pol_val)509 void EMC_StaMemConfigPC(uint32_t index , uint32_t pol_val)
510 {
511 uint32_t mask = ~(uint32_t)(_BIT(6)) ;
512 switch ( index)
513 {
514 case 0:
515 LPC_EMC->StaticConfig0 = (LPC_EMC->StaticConfig0 & mask) | pol_val;
516 break;
517 case 1:
518 LPC_EMC->StaticConfig1 = (LPC_EMC->StaticConfig1 & mask)| pol_val;
519 break;
520 case 2:
521 LPC_EMC->StaticConfig2 = (LPC_EMC->StaticConfig2 & mask) | pol_val;
522 break;
523 case 3:
524 LPC_EMC->StaticConfig3 = (LPC_EMC->StaticConfig3 & mask) | pol_val;
525 break;
526 }
527 }
528
529 /*********************************************************************//**
530 * @brief Configure the byte lane state
531 * @param[in] index index number, should be from 0 to 3
532 * @param[in] pb_val Byte lane state, should be:
533 * - 0: For reads all bits in BLSn[3:0] are HIGH.
534 * - 1: For reads all bits in BLSn[3:0] are LOW.
535 * @return None
536 **********************************************************************/
EMC_StaMemConfigPB(uint32_t index,uint32_t pb_val)537 void EMC_StaMemConfigPB(uint32_t index , uint32_t pb_val)
538 {
539 uint32_t mask = ~(uint32_t)(_BIT(7)) ;
540 switch ( index)
541 {
542 case 0:
543 LPC_EMC->StaticConfig0 = (LPC_EMC->StaticConfig0 & mask)| pb_val;
544 break;
545 case 1:
546 LPC_EMC->StaticConfig1 = (LPC_EMC->StaticConfig1 & mask)| pb_val;
547 break;
548 case 2:
549 LPC_EMC->StaticConfig2 =( LPC_EMC->StaticConfig2 & mask)| pb_val;
550 break;
551 case 3:
552 LPC_EMC->StaticConfig3 = (LPC_EMC->StaticConfig3 & mask)| pb_val;
553 break;
554 }
555 }
556
557 /*********************************************************************//**
558 * @brief Configure the extended wait value
559 * @param[in] index index number, should be from 0 to 3
560 * @param[in] ex_wait Extended wait mode, should be:
561 * - 0: Extended wait disabled.
562 * - 1: Extended wait enabled.
563 * @return None
564 **********************************************************************/
EMC_StaMemConfigEW(uint32_t index,uint32_t ex_wait)565 void EMC_StaMemConfigEW(uint32_t index , uint32_t ex_wait)
566 {
567 uint32_t mask = ~(uint32_t)(_BIT(8)) ;
568 switch ( index)
569 {
570 case 0:
571 LPC_EMC->StaticConfig0 = (LPC_EMC->StaticConfig0 & mask) | ex_wait;
572 break;
573 case 1:
574 LPC_EMC->StaticConfig1 = (LPC_EMC->StaticConfig1 & mask) | ex_wait;
575 break;
576 case 2:
577 LPC_EMC->StaticConfig2 = (LPC_EMC->StaticConfig2 & mask) | ex_wait;
578 break;
579 case 3:
580 LPC_EMC->StaticConfig3 =( LPC_EMC->StaticConfig3 & mask) | ex_wait;
581 break;
582 }
583 }
584
585 /*********************************************************************//**
586 * @brief Configure the buffer enable value
587 * @param[in] index index number, should be from 0 to 3
588 * @param[in] buf_val Buffer mode, should be:
589 * - 0: Buffer disabled.
590 * - 1: Buffer enabled.
591 * @return None
592 **********************************************************************/
EMC_StaMemConfigB(uint32_t index,uint32_t buf_val)593 void EMC_StaMemConfigB(uint32_t index , uint32_t buf_val)
594 {
595 uint32_t mask = ~(uint32_t)(_BIT(19)) ;
596 switch ( index)
597 {
598 case 0:
599 LPC_EMC->StaticConfig0 = (LPC_EMC->StaticConfig0 & mask) | buf_val;
600 break;
601 case 1:
602 LPC_EMC->StaticConfig1 = (LPC_EMC->StaticConfig1 & mask) | buf_val;
603 break;
604 case 2:
605 LPC_EMC->StaticConfig2 = (LPC_EMC->StaticConfig2 & mask) | buf_val;
606 break;
607 case 3:
608 LPC_EMC->StaticConfig3 = (LPC_EMC->StaticConfig3 & mask) | buf_val;
609 break;
610 }
611 }
612
613 /*********************************************************************//**
614 * @brief Configure the write permission
615 * @param[in] index index number, should be from 0 to 3
616 * @param[in] per_val Permission mode, should be:
617 * - 0: Write not protected.
618 * - 1: Write protected.
619 * @return None
620 **********************************************************************/
EMC_StaMemConfigpP(uint32_t index,uint32_t per_val)621 void EMC_StaMemConfigpP(uint32_t index , uint32_t per_val)
622 {
623 uint32_t mask = ~(uint32_t)(_BIT(20)) ;
624 switch ( index)
625 {
626 case 0:
627 LPC_EMC->StaticConfig0 = (LPC_EMC->StaticConfig0 & mask) | per_val;
628 break;
629 case 1:
630 LPC_EMC->StaticConfig1 = (LPC_EMC->StaticConfig1 & mask) | per_val;
631 break;
632 case 2:
633 LPC_EMC->StaticConfig2 = (LPC_EMC->StaticConfig2 & mask) | per_val;
634 break;
635 case 3:
636 LPC_EMC->StaticConfig3 = (LPC_EMC->StaticConfig3 & mask) | per_val;
637 break;
638 }
639 }
640
641 /*********************************************************************//**
642 * @brief Set the value of LPC_EMC static memory registers
643 * @param[in] index index number, should be from 0 to 3
644 * @param[in] EMC_STA_MEM_PAR Static register, should be:
645 * - EMC_STA_MEM_WAITWEN: StaticWaitWen0 register
646 * - EMC_STA_MEM_WAITOEN: StaticWaitOen0 register
647 * - EMC_STA_MEM_WAITRD: StaticWaitRd0 register
648 * - EMC_STA_MEM_WAITPAGE: StaticWaitPage0 register
649 * - EMC_STA_MEM_WAITWR: StaticWaitWr0 register
650 * - EMC_STA_MEM_WAITTURN: StaticWaitTurn0 register
651 * @return None
652 **********************************************************************/
EMC_SetStaMemoryParameter(uint32_t index,EMC_STA_MEM_PAR par,uint32_t val)653 void EMC_SetStaMemoryParameter(uint32_t index ,EMC_STA_MEM_PAR par, uint32_t val)
654 {
655 switch (index)
656 {
657 case 0:
658 switch ( par)
659 {
660 case EMC_STA_MEM_WAITWEN:
661 LPC_EMC->StaticWaitWen0 = val;
662 break;
663 case EMC_STA_MEM_WAITOEN:
664 LPC_EMC->StaticWaitOen0 = val;
665 break;
666 case EMC_STA_MEM_WAITRD:
667 LPC_EMC->StaticWaitRd0 = val;
668 break;
669 case EMC_STA_MEM_WAITPAGE:
670 LPC_EMC->StaticWaitPage0 = val;
671 break;
672 case EMC_STA_MEM_WAITWR:
673 LPC_EMC->StaticWaitWr0 = val;
674 break;
675 case EMC_STA_MEM_WAITTURN:
676 LPC_EMC->StaticWaitTurn0 = val;
677 break;
678 }
679 break;
680 case 1:
681 switch ( par)
682 {
683 case EMC_STA_MEM_WAITWEN:
684 LPC_EMC->StaticWaitWen1 = val;
685 break;
686 case EMC_STA_MEM_WAITOEN:
687 LPC_EMC->StaticWaitOen1 = val;
688 break;
689 case EMC_STA_MEM_WAITRD:
690 LPC_EMC->StaticWaitRd1 = val;
691 break;
692 case EMC_STA_MEM_WAITPAGE:
693 LPC_EMC->StaticWaitPage1 = val;
694 break;
695 case EMC_STA_MEM_WAITWR:
696 LPC_EMC->StaticWaitWr1 = val;
697 break;
698 case EMC_STA_MEM_WAITTURN:
699 LPC_EMC->StaticWaitTurn1 = val;
700 break;
701 }
702 break;
703 case 2:
704 switch ( par)
705 {
706 case EMC_STA_MEM_WAITWEN:
707 LPC_EMC->StaticWaitWen2 = val;
708 break;
709 case EMC_STA_MEM_WAITOEN:
710 LPC_EMC->StaticWaitOen2 = val;
711 break;
712 case EMC_STA_MEM_WAITRD:
713 LPC_EMC->StaticWaitRd2 = val;
714 break;
715 case EMC_STA_MEM_WAITPAGE:
716 LPC_EMC->StaticWaitPage2 = val;
717 break;
718 case EMC_STA_MEM_WAITWR:
719 LPC_EMC->StaticWaitWr2 = val;
720 break;
721 case EMC_STA_MEM_WAITTURN:
722 LPC_EMC->StaticWaitTurn2 = val;
723 break;
724 }
725 break;
726 case 3:
727 switch ( par)
728 {
729 case EMC_STA_MEM_WAITWEN:
730 LPC_EMC->StaticWaitWen3 = val;
731 break;
732 case EMC_STA_MEM_WAITOEN:
733 LPC_EMC->StaticWaitOen3 = val;
734 break;
735 case EMC_STA_MEM_WAITRD:
736 LPC_EMC->StaticWaitRd3 = val;
737 break;
738 case EMC_STA_MEM_WAITPAGE:
739 LPC_EMC->StaticWaitPage3 = val;
740 break;
741 case EMC_STA_MEM_WAITWR:
742 LPC_EMC->StaticWaitWr3 = val;
743 break;
744 case EMC_STA_MEM_WAITTURN:
745 LPC_EMC->StaticWaitTurn3 = val;
746 break;
747 }
748 break;
749 }
750 }
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