1/* 2** ################################################################### 3** Processors: LPC54114J256BD64_M4 4** LPC54114J256UK49_M4 5** 6** Compiler: IAR ANSI C/C++ Compiler for ARM 7** Reference manual: LPC5411x User manual Rev. 1.1 25 May 2016 8** Version: rev. 1.0, 2016-04-29 9** Build: b161227 10** 11** Abstract: 12** Linker file for the IAR ANSI C/C++ Compiler for ARM 13** 14** The Clear BSD License 15** Copyright 2016 Freescale Semiconductor, Inc. 16** Copyright 2016-2017 NXP 17** All rights reserved. 18** 19** Redistribution and use in source and binary forms, with or without modification, 20** are permitted (subject to the limitations in the disclaimer below) provided 21** that the following conditions are met: 22** 23** 1. Redistributions of source code must retain the above copyright notice, this list 24** of conditions and the following disclaimer. 25** 26** 2. Redistributions in binary form must reproduce the above copyright notice, this 27** list of conditions and the following disclaimer in the documentation and/or 28** other materials provided with the distribution. 29** 30** 3. Neither the name of the copyright holder nor the names of its 31** contributors may be used to endorse or promote products derived from this 32** software without specific prior written permission. 33** 34** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. 35** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 36** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 37** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 38** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 39** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 40** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 41** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 42** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 43** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 44** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 45** 46** http: www.nxp.com 47** mail: support@nxp.com 48** 49** ################################################################### 50*/ 51 52 53define symbol m_interrupts_start = 0x00000000; 54define symbol m_interrupts_end = 0x000000DF; 55 56define symbol m_text_start = 0x000000E0; 57define symbol m_text_end = 0x0002FFFF; 58 59define symbol m_data_start = 0x20000000; 60define symbol m_data_end = 0x2000FFFF; 61 62if (isdefinedsymbol(__use_shmem__)) { 63define exported symbol rpmsg_sh_mem_start = 0x20026800; 64define exported symbol rpmsg_sh_mem_end = 0x20027FFF; 65} 66 67define symbol m_sramx_start = 0x04000000; 68define symbol m_sramx_end = 0x04007FFF; 69 70define exported symbol core1_image_start = 0x00030000; 71define exported symbol core1_image_end = 0x0003FFFF; 72 73define symbol __crp_start__ = 0x000002FC; 74define symbol __crp_end__ = 0x000002FF; 75 76define symbol __ram_iap_start__ = 0x2000FFE0; 77define symbol __ram_iap_end__ = 0x2000FFFF; 78 79/* Sizes */ 80if (isdefinedsymbol(__stack_size__)) { 81 define symbol __size_cstack__ = __stack_size__; 82} else { 83 define symbol __size_cstack__ = 0x0400; 84} 85 86if (isdefinedsymbol(__heap_size__)) { 87 define symbol __size_heap__ = __heap_size__; 88} else { 89 define symbol __size_heap__ = 0x0800; 90} 91 92define exported symbol __RTT_HEAP_END = m_data_end; 93define memory mem with size = 4G; 94define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] 95 | mem:[from m_text_start to m_text_end] 96 - mem:[from __crp_start__ to __crp_end__]; 97define region DATA_region = mem:[from m_data_start to m_data_end] 98 - mem:[from __ram_iap_start__-__size_cstack__ to __ram_iap_end__]; 99define region CSTACK_region = mem:[from __ram_iap_start__-__size_cstack__ to __ram_iap_start__-1]; 100define region SRAMX_region = mem:[from m_sramx_start to m_sramx_end]; 101define region CRP_region = mem:[from __crp_start__ to __crp_end__]; 102if (isdefinedsymbol(__use_shmem__)) { 103define region rpmsg_sh_mem_region = mem:[from rpmsg_sh_mem_start to rpmsg_sh_mem_end]; 104} 105 106define block CSTACK with alignment = 8, size = __size_cstack__ { }; 107define block HEAP with alignment = 8, size = __size_heap__ { }; 108define block RW { readwrite }; 109define block ZI { zi }; 110 111define region core1_region = mem:[from core1_image_start to core1_image_end]; 112define block SEC_CORE_IMAGE_WBLOCK { section __sec_core }; 113 114initialize by copy { readwrite }; 115 116if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) 117{ 118 // Required in a multi-threaded application 119 initialize by copy with packing = none { section __DLIB_PERTHREAD }; 120} 121 122do not initialize { section .noinit }; 123if (isdefinedsymbol(__use_shmem__)) { 124do not initialize { section rpmsg_sh_mem_section }; 125} 126 127place at address mem: m_interrupts_start { readonly section .intvec }; 128place in TEXT_region { readonly }; 129place in DATA_region { block RW }; 130place in DATA_region { block ZI }; 131place in DATA_region { last block HEAP }; 132place in SRAMX_region { section sramx }; 133place in CSTACK_region { block CSTACK }; 134place in CRP_region { section .crp }; 135if (isdefinedsymbol(__use_shmem__)) { 136place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; 137} 138place in core1_region { block SEC_CORE_IMAGE_WBLOCK }; 139