1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2013-05-19 Bernard porting from LPC17xx drivers. 9 */ 10 11 #ifndef __DRV_EMAC_H__ 12 #define __DRV_EMAC_H__ 13 14 #include "board.h" 15 16 /* EMAC Memory Buffer configuration for 16K Ethernet RAM. */ 17 #define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */ 18 #define NUM_TX_FRAG 3 /* Num.of TX Fragments 3*1536= 4.6kB */ 19 #define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */ 20 21 #define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */ 22 23 24 /* MAC Configuration Register 1 */ 25 #define MAC1_REC_EN 0x00000001 /* Receive Enable */ 26 #define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */ 27 #define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */ 28 #define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */ 29 #define MAC1_LOOPB 0x00000010 /* Loop Back Mode */ 30 #define MAC1_RES_TX 0x00000100 /* Reset TX Logic */ 31 #define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */ 32 #define MAC1_RES_RX 0x00000400 /* Reset RX Logic */ 33 #define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */ 34 #define MAC1_SIM_RES 0x00004000 /* Simulation Reset */ 35 #define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */ 36 37 /* MAC Configuration Register 2 */ 38 #define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */ 39 #define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */ 40 #define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */ 41 #define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */ 42 #define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */ 43 #define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */ 44 #define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */ 45 #define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */ 46 #define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */ 47 #define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */ 48 #define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */ 49 #define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */ 50 #define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */ 51 52 /* Back-to-Back Inter-Packet-Gap Register */ 53 #define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */ 54 #define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */ 55 56 /* Non Back-to-Back Inter-Packet-Gap Register */ 57 #define IPGR_DEF 0x00000012 /* Recommended value */ 58 59 /* Collision Window/Retry Register */ 60 #define CLRT_DEF 0x0000370F /* Default value */ 61 62 /* PHY Support Register */ 63 #define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */ 64 #define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */ 65 66 /* Test Register */ 67 #define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */ 68 #define TEST_TST_PAUSE 0x00000002 /* Test Pause */ 69 #define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */ 70 71 /* MII Management Configuration Register */ 72 #define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */ 73 #define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */ 74 #define MCFG_CLK_SEL 0x0000001C /* Clock Select Mask */ 75 #define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */ 76 77 #define MCFG_CLK_DIV4 0x00000000 /* MDC = hclk / 4 */ 78 #define MCFG_CLK_DIV6 0x00000008 /* MDC = hclk / 6 */ 79 #define MCFG_CLK_DIV8 0x0000000C /* MDC = hclk / 8 */ 80 #define MCFG_CLK_DIV10 0x00000010 /* MDC = hclk / 10 */ 81 #define MCFG_CLK_DIV14 0x00000014 /* MDC = hclk / 14 */ 82 #define MCFG_CLK_DIV20 0x00000018 /* MDC = hclk / 20 */ 83 #define MCFG_CLK_DIV28 0x0000001C /* MDC = hclk / 28 */ 84 85 86 /* MII Management Command Register */ 87 #define MCMD_READ 0x00000001 /* MII Read */ 88 #define MCMD_SCAN 0x00000002 /* MII Scan continuously */ 89 90 #define MII_WR_TOUT 0x00050000 /* MII Write timeout count */ 91 #define MII_RD_TOUT 0x00050000 /* MII Read timeout count */ 92 93 /* MII Management Address Register */ 94 #define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */ 95 #define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */ 96 97 /* MII Management Indicators Register */ 98 #define MIND_BUSY 0x00000001 /* MII is Busy */ 99 #define MIND_SCAN 0x00000002 /* MII Scanning in Progress */ 100 #define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */ 101 #define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */ 102 103 /* Command Register */ 104 #define CR_RX_EN 0x00000001 /* Enable Receive */ 105 #define CR_TX_EN 0x00000002 /* Enable Transmit */ 106 #define CR_REG_RES 0x00000008 /* Reset Host Registers */ 107 #define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */ 108 #define CR_RX_RES 0x00000020 /* Reset Receive Datapath */ 109 #define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */ 110 #define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */ 111 #define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */ 112 #define CR_RMII 0x00000200 /* Reduced MII Interface */ 113 #define CR_FULL_DUP 0x00000400 /* Full Duplex */ 114 115 /* Status Register */ 116 #define SR_RX_EN 0x00000001 /* Enable Receive */ 117 #define SR_TX_EN 0x00000002 /* Enable Transmit */ 118 119 /* Transmit Status Vector 0 Register */ 120 #define TSV0_CRC_ERR 0x00000001 /* CRC error */ 121 #define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */ 122 #define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */ 123 #define TSV0_DONE 0x00000008 /* Tramsmission Completed */ 124 #define TSV0_MCAST 0x00000010 /* Multicast Destination */ 125 #define TSV0_BCAST 0x00000020 /* Broadcast Destination */ 126 #define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */ 127 #define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */ 128 #define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */ 129 #define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */ 130 #define TSV0_GIANT 0x00000400 /* Giant Frame */ 131 #define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */ 132 #define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */ 133 #define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */ 134 #define TSV0_PAUSE 0x20000000 /* Pause Frame */ 135 #define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */ 136 #define TSV0_VLAN 0x80000000 /* VLAN Frame */ 137 138 /* Transmit Status Vector 1 Register */ 139 #define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */ 140 #define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */ 141 142 /* Receive Status Vector Register */ 143 #define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */ 144 #define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */ 145 #define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */ 146 #define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */ 147 #define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */ 148 #define RSV_CRC_ERR 0x00100000 /* CRC Error */ 149 #define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */ 150 #define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */ 151 #define RSV_REC_OK 0x00800000 /* Frame Received OK */ 152 #define RSV_MCAST 0x01000000 /* Multicast Frame */ 153 #define RSV_BCAST 0x02000000 /* Broadcast Frame */ 154 #define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */ 155 #define RSV_CTRL_FRAME 0x08000000 /* Control Frame */ 156 #define RSV_PAUSE 0x10000000 /* Pause Frame */ 157 #define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */ 158 #define RSV_VLAN 0x40000000 /* VLAN Frame */ 159 160 /* Flow Control Counter Register */ 161 #define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */ 162 #define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */ 163 164 /* Flow Control Status Register */ 165 #define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */ 166 167 /* Receive Filter Control Register */ 168 #define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */ 169 #define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */ 170 #define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */ 171 #define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */ 172 #define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/ 173 #define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */ 174 #define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */ 175 #define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */ 176 177 /* Receive Filter WoL Status/Clear Registers */ 178 #define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */ 179 #define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */ 180 #define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */ 181 #define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */ 182 #define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */ 183 #define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */ 184 #define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */ 185 #define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */ 186 187 /* Interrupt Status/Enable/Clear/Set Registers */ 188 #define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */ 189 #define INT_RX_ERR 0x00000002 /* Receive Error */ 190 #define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */ 191 #define INT_RX_DONE 0x00000008 /* Receive Done */ 192 #define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */ 193 #define INT_TX_ERR 0x00000020 /* Transmit Error */ 194 #define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */ 195 #define INT_TX_DONE 0x00000080 /* Transmit Done */ 196 #define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */ 197 #define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */ 198 199 /* Power Down Register */ 200 #define PD_POWER_DOWN 0x80000000 /* Power Down MAC */ 201 202 /* RX Descriptor Control Word */ 203 #define RCTRL_SIZE 0x000007FF /* Buffer size mask */ 204 #define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */ 205 206 /* RX Status Hash CRC Word */ 207 #define RHASH_SA 0x000001FF /* Hash CRC for Source Address */ 208 #define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */ 209 210 /* RX Status Information Word */ 211 #define RINFO_SIZE 0x000007FF /* Data size in bytes */ 212 #define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */ 213 #define RINFO_VLAN 0x00080000 /* VLAN Frame */ 214 #define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */ 215 #define RINFO_MCAST 0x00200000 /* Multicast Frame */ 216 #define RINFO_BCAST 0x00400000 /* Broadcast Frame */ 217 #define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */ 218 #define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */ 219 #define RINFO_LEN_ERR 0x02000000 /* Length Error */ 220 #define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */ 221 #define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */ 222 #define RINFO_OVERRUN 0x10000000 /* Receive overrun */ 223 #define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */ 224 #define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */ 225 #define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ 226 227 #define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | \ 228 RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN) 229 230 /* TX Descriptor Control Word */ 231 #define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */ 232 #define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */ 233 #define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */ 234 #define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */ 235 #define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */ 236 #define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */ 237 #define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */ 238 239 /* TX Status Information Word */ 240 #define TINFO_COL_CNT 0x01E00000 /* Collision Count */ 241 #define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */ 242 #define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */ 243 #define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */ 244 #define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */ 245 #define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */ 246 #define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */ 247 #define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ 248 249 /* ENET Device Revision ID */ 250 #define OLD_EMAC_MODULE_ID 0x39022000 /* Rev. ID for first rev '-' */ 251 252 /* DP83848C PHY Registers */ 253 #define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */ 254 #define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */ 255 #define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */ 256 #define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */ 257 #define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */ 258 #define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */ 259 #define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */ 260 #define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */ 261 262 /* PHY Extended Registers */ 263 #define PHY_REG_STS 0x10 /* Status Register */ 264 #define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */ 265 #define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */ 266 #define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */ 267 #define PHY_REG_RECR 0x15 /* Receive Error Counter */ 268 #define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */ 269 #define PHY_REG_RBR 0x17 /* RMII and Bypass Register */ 270 #define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */ 271 #define PHY_REG_PHYCR 0x19 /* PHY Control Register */ 272 #define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */ 273 #define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */ 274 #define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */ 275 276 #define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */ 277 #define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */ 278 #define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */ 279 #define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */ 280 #define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */ 281 282 #define DP83848C_DEF_ADR 0x0F00 /* Default PHY device address */ 283 #define DP83848C_ID 0x20005C90 /* PHY Identifier */ 284 285 int lpc_emac_hw_init(void); 286 287 #endif 288