1 /* 2 * Copyright (c) 2016, Freescale Semiconductor, Inc. 3 * Copyright 2016-2017 NXP 4 * 5 * Redistribution and use in source and binary forms, with or without modification, 6 * are permitted provided that the following conditions are met: 7 * 8 * o Redistributions of source code must retain the above copyright notice, this list 9 * of conditions and the following disclaimer. 10 * 11 * o Redistributions in binary form must reproduce the above copyright notice, this 12 * list of conditions and the following disclaimer in the documentation and/or 13 * other materials provided with the distribution. 14 * 15 * o Neither the name of the copyright holder nor the names of its 16 * contributors may be used to endorse or promote products derived from this 17 * software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 #ifndef _FSL_PHY_H_ 31 #define _FSL_PHY_H_ 32 33 #include "fsl_enet.h" 34 35 /*! 36 * @addtogroup phy_driver 37 * @{ 38 */ 39 40 /******************************************************************************* 41 * Definitions 42 ******************************************************************************/ 43 44 /*! @brief PHY driver version */ 45 #define FSL_PHY_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ 46 47 /*! @brief Defines the PHY registers. */ 48 #define PHY_BASICCONTROL_REG 0x00U /*!< The PHY basic control register. */ 49 #define PHY_BASICSTATUS_REG 0x01U /*!< The PHY basic status register. */ 50 #define PHY_ID1_REG 0x02U /*!< The PHY ID one register. */ 51 #define PHY_ID2_REG 0x03U /*!< The PHY ID two register. */ 52 #define PHY_AUTONEG_ADVERTISE_REG 0x04U /*!< The PHY auto-negotiate advertise register. */ 53 #define PHY_SEPCIAL_CONTROL_REG 0x1FU /*!< The PHY control two register. */ 54 55 #define PHY_CONTROL_ID1 0x07U /*!< The PHY ID1*/ 56 57 /*! @brief Defines the mask flag in basic control register. */ 58 #define PHY_BCTL_DUPLEX_MASK 0x0100U /*!< The PHY duplex bit mask. */ 59 #define PHY_BCTL_RESTART_AUTONEG_MASK 0x0200U /*!< The PHY restart auto negotiation mask. */ 60 #define PHY_BCTL_AUTONEG_MASK 0x1000U /*!< The PHY auto negotiation bit mask. */ 61 #define PHY_BCTL_SPEED_MASK 0x2000U /*!< The PHY speed bit mask. */ 62 #define PHY_BCTL_LOOP_MASK 0x4000U /*!< The PHY loop bit mask. */ 63 #define PHY_BCTL_RESET_MASK 0x8000U /*!< The PHY reset bit mask. */ 64 65 /*!@brief Defines the mask flag of operation mode in special control register*/ 66 #define PHY_SPECIALCTL_AUTONEGDONE_MASK 0x1000U /*!< The PHY auto-negotiation complete mask. */ 67 #define PHY_SPECIALCTL_DUPLEX_MASK 0x0010U /*!< The PHY duplex mask. */ 68 #define PHY_SPECIALCTL_100SPEED_MASK 0x0008U /*!< The PHY speed mask. */ 69 #define PHY_SPECIALCTL_10SPEED_MASK 0x0004U /*!< The PHY speed mask. */ 70 #define PHY_SPECIALCTL_SPEEDUPLX_MASK 0x001cU /*!< The PHY speed and duplex mask. */ 71 72 /*! @brief Defines the mask flag in basic status register. */ 73 #define PHY_BSTATUS_LINKSTATUS_MASK 0x0004U /*!< The PHY link status mask. */ 74 75 /*! @brief Defines the mask flag in PHY auto-negotiation advertise register. */ 76 #define PHY_ALL_CAPABLE_MASK 0x1e0U 77 78 /*! @brief Defines the PHY status. */ 79 enum _phy_status 80 { 81 kStatus_PHY_SMIVisitTimeout = MAKE_STATUS(kStatusGroup_PHY, 0), /*!< ENET PHY SMI visit timeout. */ 82 }; 83 84 /*! @brief Defines the PHY link speed. This is align with the speed for ENET MAC. */ 85 typedef enum _phy_speed { 86 kPHY_Speed10M = 0U, /*!< ENET PHY 10M speed. */ 87 kPHY_Speed100M /*!< ENET PHY 100M speed. */ 88 } phy_speed_t; 89 90 /*! @brief Defines the PHY link duplex. */ 91 typedef enum _phy_duplex { 92 kPHY_HalfDuplex = 0U, /*!< ENET PHY half duplex. */ 93 kPHY_FullDuplex /*!< ENET PHY full duplex. */ 94 } phy_duplex_t; 95 96 /******************************************************************************* 97 * API 98 ******************************************************************************/ 99 100 #if defined(__cplusplus) 101 extern "C" { 102 #endif 103 104 /*! 105 * @name PHY Driver 106 * @{ 107 */ 108 109 /*! 110 * @brief Initializes PHY. 111 * 112 * This function initialize the SMI interface and initialize PHY. 113 * The SMI is the MII management interface between PHY and MAC, which should be 114 * firstly initialized before any other operation for PHY. 115 * 116 * @param base ENET peripheral base address. 117 * @param phyAddr The PHY address. 118 * @param srcClock_Hz The module clock frequency - system clock for MII management interface - SMI. 119 * @retval kStatus_Success PHY initialize success 120 * @retval kStatus_Fail PHY initialize fail 121 */ 122 status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz); 123 124 /*! 125 * @brief PHY Write function. This function write data over the SMI to 126 * the specified PHY register. This function is called by all PHY interfaces. 127 * 128 * @param base ENET peripheral base address. 129 * @param phyAddr The PHY address. 130 * @param phyReg The PHY register. 131 * @param data The data written to the PHY register. 132 * @retval kStatus_Success PHY write success 133 * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out 134 */ 135 status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data); 136 137 /*! 138 * @brief PHY Read function. This interface read data over the SMI from the 139 * specified PHY register. This function is called by all PHY interfaces. 140 * 141 * @param base ENET peripheral base address. 142 * @param phyAddr The PHY address. 143 * @param phyReg The PHY register. 144 * @param dataPtr The address to store the data read from the PHY register. 145 * @retval kStatus_Success PHY read success 146 * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out 147 */ 148 status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr); 149 150 /*! 151 * @brief Gets the PHY link status. 152 * 153 * @param base ENET peripheral base address. 154 * @param phyAddr The PHY address. 155 * @param status The link up or down status of the PHY. 156 * - true the link is up. 157 * - false the link is down. 158 * @retval kStatus_Success PHY get link status success 159 * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out 160 */ 161 status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status); 162 163 /*! 164 * @brief Gets the PHY link speed and duplex. 165 * 166 * @param base ENET peripheral base address. 167 * @param phyAddr The PHY address. 168 * @param speed The address of PHY link speed. 169 * @param duplex The link duplex of PHY. 170 * @retval kStatus_Success PHY get link speed and duplex success 171 * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out 172 */ 173 status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex); 174 175 /* @} */ 176 177 #if defined(__cplusplus) 178 } 179 #endif 180 181 /*! @}*/ 182 183 #endif /* _FSL_PHY_H_ */ 184