1 /*
2 * Copyright (c) 2006-2024 RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2024-11-26 hywing the first version.
9 *
10 */
11 #include <rtthread.h>
12
13 #ifdef BSP_USING_HWTIMER
14
15 #define LOG_TAG "drv.hwtimer"
16 #include <drv_log.h>
17 #include <rtdevice.h>
18 #include "fsl_ctimer.h"
19
20 enum
21 {
22 #ifdef BSP_USING_CTIMER0
23 TIM0_INDEX,
24 #endif
25 #ifdef BSP_USING_CTIMER1
26 TIM1_INDEX,
27 #endif
28 #ifdef BSP_USING_CTIMER2
29 TIM2_INDEX,
30 #endif
31 };
32
33 #ifdef BSP_USING_CTIMER0
34 #define TIM0_CONFIG \
35 { \
36 .tim_handle = CTIMER0, \
37 .tim_irqn = CTIMER0_IRQn, \
38 .name = "timer0", \
39 }
40 #endif /* TIM0_CONFIG */
41
42 #ifdef BSP_USING_CTIMER1
43 #define TIM1_CONFIG \
44 { \
45 .tim_handle = CTIMER1, \
46 .tim_irqn = CTIMER1_IRQn, \
47 .name = "timer1", \
48 }
49 #endif /* TIM1_CONFIG */
50
51 #ifdef BSP_USING_CTIMER2
52 #define TIM2_CONFIG \
53 { \
54 .tim_handle = CTIMER2, \
55 .tim_irqn = CTIMER2_IRQn, \
56 .name = "timer2", \
57 }
58 #endif /* TIM2_CONFIG */
59
60 struct mcxa_hwtimer
61 {
62 rt_hwtimer_t time_device;
63 CTIMER_Type* tim_handle;
64 enum IRQn tim_irqn;
65 char* name;
66 };
67
68 static struct mcxa_hwtimer mcxa_hwtimer_obj[] =
69 {
70 #ifdef BSP_USING_CTIMER0
71 TIM0_CONFIG,
72 #endif
73
74 #ifdef BSP_USING_CTIMER1
75 TIM1_CONFIG,
76 #endif
77
78 #ifdef BSP_USING_CTIMER2
79 TIM2_CONFIG,
80 #endif
81 };
82
NVIC_Configuration(void)83 static void NVIC_Configuration(void)
84 {
85 #ifdef BSP_USING_CTIMER0
86 EnableIRQ(CTIMER0_IRQn);
87 #endif
88
89 #ifdef BSP_USING_CTIMER1
90 EnableIRQ(CTIMER1_IRQn);
91 #endif
92
93 #ifdef BSP_USING_CTIMER2
94 EnableIRQ(CTIMER2_IRQn);
95 #endif
96 }
97
mcxa_ctimer_control(rt_hwtimer_t * timer,rt_uint32_t cmd,void * args)98 static rt_err_t mcxa_ctimer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args)
99 {
100 rt_err_t err = RT_EOK;
101 CTIMER_Type *hwtimer_dev;
102 hwtimer_dev = (CTIMER_Type *)timer->parent.user_data;
103
104 RT_ASSERT(timer != RT_NULL);
105
106 switch (cmd)
107 {
108 case HWTIMER_CTRL_FREQ_SET:
109 {
110 uint32_t clk;
111 uint32_t pre;
112 if(hwtimer_dev == CTIMER0) clk = CLOCK_GetCTimerClkFreq(0U);
113 if(hwtimer_dev == CTIMER1) clk = CLOCK_GetCTimerClkFreq(1U);
114 if(hwtimer_dev == CTIMER2) clk = CLOCK_GetCTimerClkFreq(2U);
115
116 pre = clk / *((uint32_t *)args) - 1;
117
118 hwtimer_dev->PR = pre;
119 }
120 break;
121 default:
122 err = -RT_ENOSYS;
123 break;
124 }
125 return err;
126 }
127
mcxa_ctimer_count_get(rt_hwtimer_t * timer)128 static rt_uint32_t mcxa_ctimer_count_get(rt_hwtimer_t *timer)
129 {
130 rt_uint32_t CurrentTimer_Count;
131 CTIMER_Type *hwtimer_dev;
132 hwtimer_dev = (CTIMER_Type *)timer->parent.user_data;
133
134 RT_ASSERT(timer != RT_NULL);
135
136 CurrentTimer_Count = hwtimer_dev->TC;
137
138 return CurrentTimer_Count;
139 }
140
mcxa_ctimer_init(rt_hwtimer_t * timer,rt_uint32_t state)141 static void mcxa_ctimer_init(rt_hwtimer_t *timer, rt_uint32_t state)
142 {
143 CTIMER_Type *hwtimer_dev;
144 ctimer_config_t cfg;
145 hwtimer_dev = (CTIMER_Type *)timer->parent.user_data;
146
147 RT_ASSERT(timer != RT_NULL);
148
149 /* Use Main clock for some of the Ctimers */
150 if(hwtimer_dev == CTIMER0) CLOCK_AttachClk(kFRO_HF_to_CTIMER0);
151 if(hwtimer_dev == CTIMER1) CLOCK_AttachClk(kFRO_HF_to_CTIMER1);
152 if(hwtimer_dev == CTIMER2) CLOCK_AttachClk(kFRO_HF_to_CTIMER2);
153
154 CTIMER_Init(hwtimer_dev, &cfg);
155
156 if (state == 1)
157 {
158 NVIC_Configuration();
159 CTIMER_GetDefaultConfig(&cfg);
160 CTIMER_Init(hwtimer_dev, &cfg);
161 }
162 }
163
mcxa_ctimer_start(rt_hwtimer_t * timer,rt_uint32_t cnt,rt_hwtimer_mode_t mode)164 static rt_err_t mcxa_ctimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t mode)
165 {
166 CTIMER_Type *hwtimer_dev;
167 hwtimer_dev = (CTIMER_Type *)timer->parent.user_data;
168 /* Match Configuration for Channel 0 */
169 ctimer_match_config_t matchCfg;
170
171 RT_ASSERT(timer != RT_NULL);
172
173 /* Configuration*/
174 matchCfg.enableCounterReset = true;
175 matchCfg.enableCounterStop = (mode == HWTIMER_MODE_ONESHOT) ? true : false;;
176 matchCfg.matchValue = cnt;
177 matchCfg.outControl = kCTIMER_Output_NoAction;
178 matchCfg.outPinInitState = false;
179 matchCfg.enableInterrupt = true;
180
181 CTIMER_SetupMatch(hwtimer_dev, kCTIMER_Match_1, &matchCfg);
182
183 NVIC_Configuration();
184
185 CTIMER_StartTimer(hwtimer_dev);
186
187 return RT_EOK;
188 }
189
mcxa_ctimer_stop(rt_hwtimer_t * timer)190 static void mcxa_ctimer_stop(rt_hwtimer_t *timer)
191 {
192 CTIMER_Type *hwtimer_dev;
193 hwtimer_dev = (CTIMER_Type *)timer->parent.user_data;
194
195 RT_ASSERT(timer != RT_NULL);
196
197 CTIMER_StopTimer(hwtimer_dev);
198 }
199
200 static const struct rt_hwtimer_ops mcxa_hwtimer_ops =
201 {
202 .init = mcxa_ctimer_init,
203 .start = mcxa_ctimer_start,
204 .stop = mcxa_ctimer_stop,
205 .count_get = mcxa_ctimer_count_get,
206 .control = mcxa_ctimer_control,
207 };
208
209 static const struct rt_hwtimer_info mcxa_hwtimer_info =
210 {
211 96000000, /* the maximum count frequency can be set */
212 6103, /* the minimum count frequency can be set */
213 0xFFFFFFFF,
214 HWTIMER_CNTMODE_UP,
215 };
216
rt_hw_hwtimer_init(void)217 int rt_hw_hwtimer_init(void)
218 {
219 int i = 0;
220 int result = RT_EOK;
221
222 for (i = 0; i < sizeof(mcxa_hwtimer_obj) / sizeof(mcxa_hwtimer_obj[0]); i++)
223 {
224 mcxa_hwtimer_obj[i].time_device.info = &mcxa_hwtimer_info;
225 mcxa_hwtimer_obj[i].time_device.ops = &mcxa_hwtimer_ops;
226 if (rt_device_hwtimer_register(&mcxa_hwtimer_obj[i].time_device,
227 mcxa_hwtimer_obj[i].name, mcxa_hwtimer_obj[i].tim_handle) == RT_EOK)
228 {
229 LOG_D("%s register success", mcxa_hwtimer_obj[i].name);
230 }
231 else
232 {
233 LOG_E("%s register failed", mcxa_hwtimer_obj[i].name);
234 result = -RT_ERROR;
235 }
236 }
237
238 return result;
239 }
240
241 INIT_DEVICE_EXPORT(rt_hw_hwtimer_init);
242
243 #ifdef BSP_USING_CTIMER0
CTIMER0_IRQHandler(void)244 void CTIMER0_IRQHandler(void)
245 {
246 rt_interrupt_enter();
247 uint32_t int_stat;
248 /* Get Interrupt status flags */
249 int_stat = CTIMER_GetStatusFlags(CTIMER0);
250 /* Clear the status flags that were set */
251 CTIMER_ClearStatusFlags(CTIMER0, int_stat);
252 rt_device_hwtimer_isr(&mcxa_hwtimer_obj[TIM0_INDEX].time_device);
253 rt_interrupt_leave();
254 }
255 #endif /* BSP_USING_HWTIMER0 */
256
257 #ifdef BSP_USING_CTIMER1
CTIMER1_IRQHandler(void)258 void CTIMER1_IRQHandler(void)
259 {
260 rt_interrupt_enter();
261 uint32_t int_stat;
262 /* Get Interrupt status flags */
263 int_stat = CTIMER_GetStatusFlags(CTIMER1);
264 /* Clear the status flags that were set */
265 CTIMER_ClearStatusFlags(CTIMER1, int_stat);
266 rt_device_hwtimer_isr(&mcxa_hwtimer_obj[TIM1_INDEX].time_device);
267 rt_interrupt_leave();
268 }
269 #endif /* BSP_USING_HWTIMER1 */
270
271 #ifdef BSP_USING_CTIMER2
CTIMER2_IRQHandler(void)272 void CTIMER2_IRQHandler(void)
273 {
274 rt_interrupt_enter();
275 uint32_t int_stat;
276 /* Get Interrupt status flags */
277 int_stat = CTIMER_GetStatusFlags(CTIMER2);
278 /* Clear the status flags that were set */
279 CTIMER_ClearStatusFlags(CTIMER2, int_stat);
280 rt_device_hwtimer_isr(&mcxa_hwtimer_obj[TIM2_INDEX].time_device);
281 rt_interrupt_leave();
282 }
283 #endif /* BSP_USING_HWTIMER2 */
284
285
286 #endif /* BSP_USING_HWTIMER */
287