1 /*
2 * Copyright (c) 2006-2024 RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2024-08-1 hywing The first version for MCXA
9 */
10 #include "rtdevice.h"
11 #include "drv_spi.h"
12 #include "fsl_lpspi.h"
13
14
15 #ifdef RT_USING_SPI
16
17 #define DBG_TAG "drv.spi"
18 #define DBG_LVL DBG_INFO
19 #include <rtdbg.h>
20
21 enum
22 {
23 #ifdef BSP_USING_SPI0
24 SPI0_INDEX,
25 #endif
26 #ifdef BSP_USING_SPI1
27 SPI1_INDEX,
28 #endif
29 };
30
31 struct lpc_spi
32 {
33 struct rt_spi_bus parent;
34 LPSPI_Type *LPSPIx;
35 clock_attach_id_t clock_attach_id;
36 clock_div_name_t clock_div_name;
37 clock_name_t clock_name;
38
39
40 rt_sem_t sem;
41 char *name;
42 };
43
44 static struct lpc_spi lpc_obj[] =
45 {
46 #ifdef BSP_USING_SPI0
47 {
48 .LPSPIx = LPSPI0,
49 #if (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN))
50 kFRO_LF_DIV_to_LPSPI0,
51 #else
52 .clock_attach_id = kFRO12M_to_LPSPI0,
53 #endif
54 .clock_div_name = kCLOCK_DivLPSPI0,
55 .clock_name = kCLOCK_Fro12M,
56 .name = "spi0",
57 },
58 #endif
59 #ifdef BSP_USING_SPI1
60 {
61 .LPSPIx = LPSPI1,
62 #if (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN))
63 kFRO_LF_DIV_to_LPSPI1,
64 #else
65 .clock_attach_id = kFRO12M_to_LPSPI1,
66 #endif
67 .clock_div_name = kCLOCK_DivLPSPI1,
68 .clock_name = kCLOCK_Fro12M,
69 .name = "spi1",
70 },
71 #endif
72 };
73
rt_hw_spi_device_attach(const char * bus_name,const char * device_name,rt_uint32_t pin)74 rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_uint32_t pin)
75 {
76 struct rt_spi_device *spi_device = rt_malloc(sizeof(struct rt_spi_device));
77 if (!spi_device)
78 {
79 return -RT_ENOMEM;
80 }
81
82 return rt_spi_bus_attach_device_cspin(spi_device, device_name, bus_name, pin, NULL);
83 }
84
spi_configure(struct rt_spi_device * device,struct rt_spi_configuration * cfg)85 static rt_err_t spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg)
86 {
87 return RT_EOK;
88 }
89
90
91
spixfer(struct rt_spi_device * device,struct rt_spi_message * message)92 static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
93 {
94 lpspi_transfer_t transfer = {0};
95 status_t status;
96
97 RT_ASSERT(device != RT_NULL);
98 RT_ASSERT(device->bus != RT_NULL);
99 RT_ASSERT(device->bus->parent.user_data != RT_NULL);
100
101 struct lpc_spi *spi = device->bus->parent.user_data;
102
103 if (message->cs_take)
104 {
105 rt_pin_write(device->cs_pin, PIN_LOW);
106 }
107
108 transfer.dataSize = message->length;
109 transfer.rxData = (uint8_t *)(message->recv_buf);
110 transfer.txData = (uint8_t *)(message->send_buf);
111 transfer.configFlags = kLPSPI_MasterPcs0;
112
113 // Use blocking transfer instead of DMA
114 status = LPSPI_MasterTransferBlocking(spi->LPSPIx, &transfer);
115
116 if (message->cs_release)
117 {
118 rt_pin_write(device->cs_pin, PIN_HIGH);
119 }
120
121 if (status != kStatus_Success)
122 {
123 return 0; // Transfer failed
124 }
125
126 return message->length;
127 }
128
129
130 static struct rt_spi_ops lpc_spi_ops =
131 {
132 .configure = spi_configure,
133 .xfer = spixfer
134 };
135
rt_hw_spi_init(void)136 int rt_hw_spi_init(void)
137 {
138 int i;
139
140 for (i = 0; i < ARRAY_SIZE(lpc_obj); i++)
141 {
142 CLOCK_SetClockDiv(lpc_obj[i].clock_div_name, 1u);
143 CLOCK_AttachClk(lpc_obj[i].clock_attach_id);
144
145 lpc_obj[i].parent.parent.user_data = &lpc_obj[i];
146 lpc_obj[i].sem = rt_sem_create("sem_spi", 0, RT_IPC_FLAG_FIFO);
147
148 lpspi_master_config_t masterConfig;
149 LPSPI_MasterGetDefaultConfig(&masterConfig);
150 masterConfig.baudRate = 10 * 1000 * 1000;
151 masterConfig.pcsToSckDelayInNanoSec = 1000000000U / masterConfig.baudRate * 1U;
152 masterConfig.lastSckToPcsDelayInNanoSec = 1000000000U / masterConfig.baudRate * 1U;
153 masterConfig.betweenTransferDelayInNanoSec = 1000000000U / masterConfig.baudRate * 1U;
154
155 LPSPI_MasterInit(lpc_obj[i].LPSPIx, &masterConfig, CLOCK_GetFreq(lpc_obj[i].clock_name));
156
157 rt_spi_bus_register(&lpc_obj[i].parent, lpc_obj[i].name, &lpc_spi_ops);
158 }
159 return RT_EOK;
160 }
161 INIT_DEVICE_EXPORT(rt_hw_spi_init);
162
163 #endif /* RT_USING_SPI */
164
165