1/*
2** ###################################################################
3**     Processors:          MCXN236VDF
4**                          MCXN236VNL
5**
6**     Compiler:            IAR ANSI C/C++ Compiler for ARM
7**     Reference manual:    MCXN23XRM
8**     Version:             rev. 1.0, 2021-08-03
9**     Build:               b240320
10**
11**     Abstract:
12**         Linker file for the IAR ANSI C/C++ Compiler for ARM
13**
14**     Copyright 2016 Freescale Semiconductor, Inc.
15**     Copyright 2016-2024 NXP
16**     SPDX-License-Identifier: BSD-3-Clause
17**
18**     http:                 www.nxp.com
19**     mail:                 support@nxp.com
20**
21** ###################################################################
22*/
23
24
25/* USB BDT size */
26define symbol usb_bdt_size             = 0x0;
27/* Stack and Heap Sizes */
28if (isdefinedsymbol(__stack_size__)) {
29  define symbol __size_cstack__        = __stack_size__;
30} else {
31  define symbol __size_cstack__        = 0x0400;
32}
33
34if (isdefinedsymbol(__heap_size__)) {
35  define symbol __size_heap__          = __heap_size__;
36} else {
37  define symbol __size_heap__          = 0x2000;
38}
39
40define symbol m_interrupts_start               = 0x00000000;
41define symbol m_interrupts_end                 = 0x000003FF;
42
43define symbol m_text_start                     = 0x00000400;
44define symbol m_text_end                       = 0x000FFFFF;
45
46define symbol m_data_start                     = 0x20000000;
47define symbol m_data_end                       = 0x20037FFF;
48
49define symbol m_sramx_start                    = 0x04000000;
50define symbol m_sramx_end                      = 0x04017FFF;
51
52
53define memory mem with size = 4G;
54
55define region TEXT_region             = mem:[from m_interrupts_start to m_interrupts_end]
56                                      | mem:[from m_text_start to m_text_end];
57
58define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__] |
59                            mem:[from m_sramx_start to m_sramx_end];
60define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
61
62define block CSTACK        with alignment = 8, size = __size_cstack__   { };
63define block HEAP          with alignment = 8, size = __size_heap__     { };
64define block RW            { readwrite };
65define block ZI            { zi };
66define block NCACHE_VAR    { section NonCacheable , section NonCacheable.init };
67define block QACCESS_CODE  { section CodeQuickAccess };
68define block QACCESS_DATA  { section DataQuickAccess };
69
70initialize by copy { readwrite, section .textrw };
71
72if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
73{
74  /* Required in a multi-threaded application */
75  initialize by copy with packing = none { section __DLIB_PERTHREAD };
76}
77
78place at address mem: m_interrupts_start    { readonly section .intvec };
79place in TEXT_region                        { readonly };
80place in DATA_region                        { block RW };
81place in DATA_region                        { block ZI };
82place in DATA_region                        { last block HEAP };
83place in CSTACK_region                      { block CSTACK };
84place in DATA_region                        { block NCACHE_VAR };
85place in DATA_region                        { block QACCESS_CODE };
86place in DATA_region                        { block QACCESS_DATA };
87