1 /*
2 * Copyright (c) 2006-2024, RT-Thread Development Team
3 * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 *
7 * Change Logs:
8 * Date Author Notes
9 * 2024-01-29 yandld first implementation
10 */
11
12 #include <rthw.h>
13 #include <rtthread.h>
14
15 #include "board.h"
16 #include "clock_config.h"
17 #include "pin_mux.h"
18 #include "drv_uart.h"
19 #include "fsl_port.h"
20 #include "fsl_cache_lpcac.h"
21
22 /**
23 * This is the timer interrupt service routine.
24 *
25 */
SysTick_Handler(void)26 void SysTick_Handler(void)
27 {
28 /* enter interrupt */
29 rt_interrupt_enter();
30
31 rt_tick_increase();
32
33 /* leave interrupt */
34 rt_interrupt_leave();
35 }
36
37 /**
38 * This function will initial board.
39 */
rt_hw_board_init()40 void rt_hw_board_init()
41 {
42 /* Hardware Initialization */
43 BOARD_InitBootPins();
44 L1CACHE_EnableCodeCache();
45
46 CLOCK_EnableClock(kCLOCK_Freqme);
47 CLOCK_EnableClock(kCLOCK_InputMux);
48
49 CLOCK_EnableClock(kCLOCK_Port0);
50 CLOCK_EnableClock(kCLOCK_Port1);
51 CLOCK_EnableClock(kCLOCK_Port2);
52 CLOCK_EnableClock(kCLOCK_Port3);
53 CLOCK_EnableClock(kCLOCK_Port4);
54
55 CLOCK_EnableClock(kCLOCK_Gpio0);
56 CLOCK_EnableClock(kCLOCK_Gpio1);
57 CLOCK_EnableClock(kCLOCK_Gpio2);
58 CLOCK_EnableClock(kCLOCK_Gpio3);
59 CLOCK_EnableClock(kCLOCK_Gpio4);
60
61 CLOCK_EnableClock(kCLOCK_Pint);
62 CLOCK_EnableClock(kCLOCK_Flexcan0);
63 CLOCK_EnableClock(kCLOCK_Flexcan1);
64
65 CLOCK_AttachClk(kFRO_HF_to_ADC0);
66 CLOCK_SetClkDiv(kCLOCK_DivAdc0Clk, 1u);
67
68 /* enable VREF */
69 SPC0->ACTIVE_CFG1 |= 0xFFFFFFFF;
70
71 CLOCK_EnableClock(kCLOCK_Dma0);
72 CLOCK_EnableClock(kCLOCK_Dma1);
73
74 edma_config_t userConfig = {0};
75 EDMA_GetDefaultConfig(&userConfig);
76 EDMA_Init(DMA0, &userConfig);
77 EDMA_Init(DMA1, &userConfig);
78
79 /* This init has finished in secure side of TF-M */
80 BOARD_InitBootClocks();
81
82 CLOCK_SetupClk16KClocking(kCLOCK_Clk16KToAll);
83
84 CLOCK_AttachClk(kPLL0_to_CTIMER0);
85 CLOCK_AttachClk(kPLL0_to_CTIMER1);
86 CLOCK_AttachClk(kPLL0_to_CTIMER2);
87 CLOCK_AttachClk(kPLL0_to_CTIMER3);
88 CLOCK_AttachClk(kPLL0_to_CTIMER4);
89 CLOCK_SetClkDiv(kCLOCK_DivCtimer0Clk, 1u);
90 CLOCK_SetClkDiv(kCLOCK_DivCtimer1Clk, 1u);
91 CLOCK_SetClkDiv(kCLOCK_DivCtimer2Clk, 1u);
92 CLOCK_SetClkDiv(kCLOCK_DivCtimer3Clk, 1u);
93 CLOCK_SetClkDiv(kCLOCK_DivCtimer4Clk, 1u);
94
95 SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
96 /* set pend exception priority */
97 NVIC_SetPriority(PendSV_IRQn, (1 << __NVIC_PRIO_BITS) - 1);
98
99 /*init uart device*/
100 rt_hw_uart_init();
101
102 #if defined(BSP_USING_LEDG_PWM) && defined(BSP_USING_PWM)
103 PORT_SetPinMux(PORT0, 27, kPORT_MuxAlt4);
104 #endif
105
106 #if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
107 rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
108 #endif
109
110 #ifdef RT_USING_COMPONENTS_INIT
111 /* initialization board with RT-Thread Components */
112 rt_components_board_init();
113 #endif
114
115 #ifdef RT_USING_HEAP
116 rt_kprintf("sram heap, begin: 0x%p, end: 0x%p\n", HEAP_BEGIN, HEAP_END);
117 rt_system_heap_init((void *)HEAP_BEGIN, (void *)(HEAP_END));
118 #endif
119 }
120
121 /**
122 * This function will called when memory fault.
123 */
MemManage_Handler(void)124 void MemManage_Handler(void)
125 {
126 extern void HardFault_Handler(void);
127
128 rt_kprintf("Memory Fault!\n");
129 HardFault_Handler();
130 }
131
rt_hw_us_delay(rt_uint32_t us)132 void rt_hw_us_delay(rt_uint32_t us)
133 {
134 rt_uint32_t ticks;
135 rt_uint32_t told, tnow, tcnt = 0;
136 rt_uint32_t reload = SysTick->LOAD;
137
138 ticks = us * reload / (1000000 / RT_TICK_PER_SECOND);
139 told = SysTick->VAL;
140 while (1)
141 {
142 tnow = SysTick->VAL;
143 if (tnow != told)
144 {
145 if (tnow < told)
146 {
147 tcnt += told - tnow;
148 }
149 else
150 {
151 tcnt += reload - tnow + told;
152 }
153 told = tnow;
154 if (tcnt >= ticks)
155 {
156 break;
157 }
158 }
159 }
160 }
161