1 /*
2  * Copyright (c) 2006-2021, RT-Thread Development Team
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  *
6  * Email: opensource_embedded@phytium.com.cn
7  *
8  * Change Logs:
9  * Date        Author       Notes
10  * 2024/07/15  zhangyan     first commit
11  */
12 #include "rtconfig.h"
13 #ifdef RT_USING_SMP
14 #include <rtthread.h>
15 #include <rtdevice.h>
16 #include <string.h>
17 #include "fparameters.h"
18 #include "ftypes.h"
19 #include "board.h"
20 #include <rtdbg.h>
21 #include "interrupt.h"
22 #include <rtdef.h>
23 #include "rtatomic.h"
24 
25 #define RT_TEST_IPI                     3
26 
27 struct rt_thread core_test_thread[RT_CPUS_NR];
28 
29 static char *core_thread_name[] =
30 {
31     "core0_sgi_test",
32     "core1_sgi_test",
33     "core2_sgi_test",
34     "core3_sgi_test",
35     "core4_sgi_test",
36     "core5_sgi_test",
37     "core6_sgi_test",
38     "core7_sgi_test",
39 };
40 static rt_uint8_t core_stack[RT_CPUS_NR][4096];
41 
smp_test_ipi_handle(int vector,void * param)42 static rt_isr_handler_t smp_test_ipi_handle(int vector, void *param)
43 {
44     rt_int32_t cpu_id = rt_hw_cpu_id();
45     rt_kprintf("smp_test_ipi_handle, cpu_id = %d\n", cpu_id);
46 }
47 
core_thread(void * parameter)48 static void core_thread(void *parameter)
49 {
50     rt_base_t level;
51     rt_int32_t cpu_id = rt_hw_cpu_id();
52 
53     /* code */
54     level = rt_cpus_lock();
55     rt_hw_ipi_handler_install(RT_TEST_IPI, smp_test_ipi_handle);
56     rt_hw_interrupt_umask(RT_TEST_IPI);
57     rt_kprintf("core%d, rt_hw_interrupt_umask(RT_TEST_IPI) successfully.\n", cpu_id);
58     rt_cpus_unlock(level);
59 }
60 
demo_core_test(void)61 void demo_core_test(void)
62 {
63     rt_ubase_t i;
64     rt_ubase_t cpu_id = 0;
65     rt_kprintf("demo_core%d \n", rt_hw_cpu_id());
66     for (i = 0; i < RT_CPUS_NR; i++)
67     {
68         cpu_id = i;
69         rt_thread_init(&core_test_thread[i],
70                        core_thread_name[i],
71                        core_thread,
72                        RT_NULL,
73                        &core_stack[i],
74                        2048,
75                        20,
76                        32);
77 
78         rt_thread_control(&core_test_thread[i], RT_THREAD_CTRL_BIND_CPU, (void *)cpu_id);
79         rt_thread_startup(&core_test_thread[i]);
80         rt_thread_mdelay(100);
81     }
82 }
83 
84 /* this function will toggle output pin and test intr of input pin */
smp_sgi_test_thread(void * parameter)85 static void smp_sgi_test_thread(void *parameter)
86 {
87     rt_uint32_t cpu_mask = 0;
88 
89     for (rt_uint32_t i = 0; i < RT_CPUS_NR; i++)
90     {
91         cpu_mask = (1 << i);
92         rt_hw_ipi_send(RT_TEST_IPI, cpu_mask);
93         rt_thread_mdelay(10);
94     }
95 }
96 
smp_sgi_sample(int argc,char * argv[])97 void smp_sgi_sample(int argc, char *argv[])
98 {
99     rt_thread_t thread;
100     rt_err_t res;
101     demo_core_test();
102     rt_thread_mdelay(100);
103     thread = rt_thread_create("smp_test_thread", smp_sgi_test_thread, RT_NULL, 4096, 25, 10);
104     res = rt_thread_startup(thread);
105     RT_ASSERT(res == RT_EOK);
106 }
107 
108 MSH_CMD_EXPORT(smp_sgi_sample, smp toggle sgi sample.);
109 
110 #endif